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Part Manufacturer Description Datasheet Download Buy Part
LT1796IS8 Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1796CN8 Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
LT1796IS8#TRPBF Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C
LT1796CS8#TR Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: 0°C to 70°C
LT1796CN8#PBF Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: PDIP; Pins: 8; Temperature Range: 0°C to 70°C
LT1796IS8#TR Linear Technology LT1796 - Overvoltage Fault Protected CAN Transceiver; Package: SO; Pins: 8; Temperature Range: -40°C to 85°C

64M-BIT Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
2002 - internal block diagram of mobile phone

Abstract: 64M-BIT mobile phone circuit diagram stacked MCP 32M-BIT 32-Mbit
Text: with similar configuration. MB84VD23280FA : 64M-bit NOR-type dual-operation flash memory8M-bit SRAM MB84VD23381FJ : 64M-bit NOR-type dual-operation flash memory16M-bit Mobile FCRAM*2*3 MB84VD23481FJ : 64M-bit NOR-type dual-operation flash memory32M-bit Mobile FCRAM MB84VD23581FJ : 64M-bit NOR-type dual-operation flash memory64M-bit Mobile FCRAM The 64M-bit NOR-type dual-operation flash memory mounted in all these , the mobile devices. We have developed our own 16M/32M/ 64M-bit Mobile FCRAMs as ASMs *4 for mobile


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PDF 64M-bit internal block diagram of mobile phone mobile phone circuit diagram stacked MCP 32M-BIT 32-Mbit
TSOP SDRAM

Abstract: No abstract text available
Text: Module DESCRIPTION: ValueRam's KVR133X72RC3/1024 is a 128M x 72- bit (1024MB) PC133 CL3 (CAS Latency 3) Registered SDRAM (Synchronous DRAM) memory module. The components on this module include thirty-six 64M x 4- bit , ) 94 V - 0 64M x 4- Bit TSOP 16M x 4- Bit TSOP 64M x 4- Bit TSOPx 4- Bit 16M TSOP 64M x 4- Bit TSOPx 4- Bit 16M TSOP 64M x 4- Bit TSOP 4- Bit 16M x TSOP 64M x 4- Bit TSOP x 4- Bit 16M TSOP 64M x 4- Bit TSOP x 4- Bit 16M TSOP 64M x 4- Bit TSOP 16M x 4- Bit TSOP 64M x 4- Bit TSOP 16M x 4- Bit


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PDF KVR133X72RC3/1024 PC133 168-Pin KVR133X72RC3/1024 72-bit 1024MB) 1000ns TSOP SDRAM
Not Available

Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE 64M-BIT VIRTUAL CHANNEL SDRAM VERSION 1.1 Description The 64 Mbit Virtual Channel (VC) SDRAM is , 9 7 NEC 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE Ordering Information ( 1/2 , ) NEC 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE J Low Power Operation 1 _ Part number , 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE Part Number [ x4, x8 ] ßPÖ4 5 65 8 2 1 G5


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PDF 64M-BIT S54G5-80-9JF
32M-BIT

Abstract: No abstract text available
Text: MB82D02172A / MB82D04172 New products 32M- bit / 64M-bit Mobile FCRAM TM MB82D02172A / MB82D04172 FUJITSU has developed 32M- bit and 64M-bit Mobile FCRAMTMs, these memories provide large-density , developing a largedensity 64M-bit Mobile FCRAM with the same high access speed of 65ns and low power , developed: Second-generation 32M- bit product: MB82D02172A First-generation 64M-bit product: MB82D04172 , ) / 16M- bit ( 64M-bit product) data can be retained. In the conventional power down-mode (SLEEP mode


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PDF MB82D02172A MB82D04172 32M-bit 64M-bit PARTIAL16M-bit MB82D02172A
ECC 84

Abstract: No abstract text available
Text: Module DESCRIPTION: ValueRam's KVR100X72RC2/512 is a 64M x 72- bit (512MB) PC100 CL2 (CAS Latency 2) ECC Registered SDRAM (Synchronous DRAM) memory module. The components on this module include eighteen 64M x 4- bit (16M x 4- Bit x 4 bank) SDRAM CL2 PC100 components in TSOP packages. This 168-pin DIMM uses gold , 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP REG Note: All


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PDF KVR100X72RC2/512 PC100 168-Pin KVR100X72RC2/512 72-bit 512MB) 168-pin 1000ns ECC 84
1998 - Not Available

Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM 64M-BIT VIRTUAL CHANNEL SDRAM Description The 64M-bit Virtual Channel (VC) SDRAM is implemented to be 100% pin and package compatible to , revised points. © 1997,1998 64M-BIT VIRTUAL CHANNEL SDRAM 5 Ordering Information (1/2 , 143 133 100 66 1 2 2M x 16 x 2 143 133 100 66 1 Note Under development 2 64M-BIT , 32 Channels Interface 1 : LVTTL 2 : SSTL Note Note Reserved 3 64M-BIT VIRTUAL CHANNEL


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PDF 64M-BIT
TP032

Abstract: SC 2262
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE 64M-BIT VIRTUAL CHANNEL SDRAM VERSION 2.0 Description The 64 M-bit Virtual Channel (VC) SDRAM is , mark show s m ajor revised points. © NECCorporation 1997 NEC Ordering Information 64M-BIT , read latency Note Under developm ent 2 Preliminary Data Sheet NEC 64M-BIT VIRTUAL , 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE [ x4, x8 ] /iPD4 5 NEC Memory Synchronous DRAM


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PDF 64M-BIT TP032 SC 2262
s6665

Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM with DOUBLE DATA RATE 64M-BIT VIRTUAL CHANNEL SDRAM VERSION 0.1 Description The 64 M-bit Virtual Channel (VC) SDRAM , Corporation 1998 NEC 64M-BIT VIRTUAL CHANNEL SDRAM with DOUBLE DATA RATE Ordering Information Part , Preliminary Data Sheet NEC 64M-BIT VIRTUAL CHANNEL SDRAM with DOUBLE DATA RATE Part Number [ x4 , : SSTL Note Reserve Preliminary Data Sheet 3 NEC 64M-BIT VIRTUAL CHANNEL SDRAM with


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PDF 64M-BIT 66-pin s6665
D4565821G5-A70-9J

Abstract: No abstract text available
Text: DA TA SH EE T NEC MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM 64M-BIT VIRTUAL , Corporation 1997,1998 NEC Ordering Information 64M-BIT VIRTUAL CHANNEL SDRAM ( 1/ 2 ) Part number , Number 64M-BIT VIRTUAL CHANNEL SDRAM [ x4, x8 ] ¿/PD4 5 NEC Memory 65 8 2 1 G5 - A70L Low , 64M-BIT VIRTUAL CHANNEL SDRAM [ X16, X32 ] ¿¿PD4 5 NEC Memory Synchronous DRAM 65 16 1 G5 - , d 4 NEC Pin Configurations /xxx indicates active low signal. 64M-BIT VIRTUAL CHANNEL


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PDF 64M-BIT D4565821G5-A70-9J
1998 - Not Available

Abstract: No abstract text available
Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE 64M-BIT VIRTUAL CHANNEL SDRAM VERSION 1.2 Description The 64 Mbit Virtual Channel (VC) SDRAM is , February 1998 NS CP(K) Printed in Japan The mark · shows major revised points. © 1997 64M-BIT , Preliminary Data Sheet 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE · [ Low Power Operation ]Note , Preliminary Data Sheet 3 64M-BIT VIRTUAL CHANNEL SDRAM SINGLE DATA RATE Part Number [ x4, x8 ] µ


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PDF 64M-BIT
Not Available

Abstract: No abstract text available
Text: Module DESCRIPTION: ValueRam's KVR133X72RC3/512 is a 64M x 72- bit (512MB) PC133 CL3 (CAS Latency 3) Registered SDRAM (Synchronous DRAM) memory module. The components on this module include eighteen 64M x 4- bit , (operating) 94 V - 0 R .078 2 PLCS R .040 2 PLCS 168 85 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP 64M x 4- Bit TSOP REG Note: All measurements are in decimal inches


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PDF KVR133X72RC3/512 PC133 168-Pin KVR133X72RC3/512 72-bit 512MB) 1000ns
1997 - 3164165

Abstract: TSOP-II-32 marking AJ 7 64M-DRAM 3165165AT TSOPII-50 cmos dram 8m x 16 hyb3165165 GPJ05855 3164805
Text: technology highlights Package outline dimension Packing 10.96 Info64M3.doc 64M-Bit DRAM This information note is intended to provide technical information on the SIEMENS second generation 64M-bit , assembled in industry standard SOJ and TSOPII packages. The second generation 64M-Bit DRAMs utilise a 0.35 , 16M x 4 8M x 8 4M x 16 2 64M-Bit DRAM PACKAGE OUTLINE DRAWINGS The SIEMENS 64M , vaporphase or reflow soldering. SIEMENS 64M-DRAMs are available in either trays or tubes. 3 64M-Bit


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PDF Info64M3 64M-Bit HYB3164 400/800/160AJ/AT 405/805/165AJ/AT 400mil SOJ-24 3164165 TSOP-II-32 marking AJ 7 64M-DRAM 3165165AT TSOPII-50 cmos dram 8m x 16 hyb3165165 GPJ05855 3164805
2002 - Not Available

Abstract: No abstract text available
Text: New products MB84VZ064A Stacked MCP Mounted with Two 64M-bit NOR-type Flash Memories, a , 's largest memory density, mounted with two 64M-bit NOR-type flash memories, a 32M- bit mobile FCRAMTM, and , MB84VZ064A, a quadruple-stacked multi-chip package (MCP) mounted with two 64M-bit NOR-type flash memories , memory required for a cellular phone in a single package by fitting the package with two 64M-bit flash , Main Characteristics Item MB84VZ064A 64M-bit NOR-type flash memory×2 32M- bit mobile FCRAM


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PDF MB84VZ064A 64M-bit 32M-bit MB84VZ064A, 40REF 80REF
A17a

Abstract: A21A A18A internal block diagram of mobile phone MCP market CE-2Ra 92PIN MB84VZ128A MB84VY6A4A1 A22A
Text: 64M-bit NOR-type Flash memory 64M-bit Mobile FCRAMTM*1 32M- bit Mobile FCRAM 128M- bit NOR-type dual-operation Flash memory with page-read mode (×16) 64M-bit NOR-type dual-operation Flash memory (×16) 64M-bit Mobile FCRAM (×16) 32M- bit Mobile FCRAM (×16) Bus B (Baseband Block/Lower , Standby Current Random35mA at maximum Page15mA at maximum 5A at maximum 64M-bit NOR-type dual operation Flash Memory 70ns 30mA at maximum 5A at maximum 64M-bit Mobile FCRAM 70ns 25mA


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PDF MB84VY6A4A1 MB84VY6A4A1 40REF 80REF A17a A21A A18A internal block diagram of mobile phone MCP market CE-2Ra 92PIN MB84VZ128A A22A
KVR133X72RC3L

Abstract: ecc 808
Text: Memory Module Specification KVR133X72RC3L/512 512MB 64M x 72- Bit PC133 Registered CL3 Low Profile ECC 168-Pin DIMM DESCRIPTION: This document describes ValueRAM's 64M x 72- bit (512MB) CAS Latency 3 (CL3) Registered SDRAM (Synchronous DRAM) PC133 low profile memory module. The components on this module include eighteen 64M x 4- bit (16M x 4- bit x 4 Bank) PC133 SDRAM (8K refresh) in TSOP packages. This 168-pin DIMM uses gold contact fingers and requires +3.3V. The electrical and mechanical


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PDF KVR133X72RC3L/512 512MB 72-Bit PC133 168-Pin 72-bit 512MB) KVR133X72RC3L ecc 808
Not Available

Abstract: No abstract text available
Text: TMS664414, TMS664814, TMS664164 64M-BIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS69Q - , AC TV TMS664414, TMS664814, TMS664164 64M-BIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS69Ö , BOX 1443 · HOUSTON TEXAS 77251-1443 TMS664414, TMS664814, TMS664164 64M-BIT SYNCHRONOUS DYNAMIC , TMS664414, TMS664814, TMS664164 64M-BIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS69Q - DECEM BER 1996 , HOUSTON^ TEXAS 77251-1443 TMS664414, TMS664814, TMS664164 64M-BIT SYNCHRONOUS DYNAMIC RANDOM-ACCESS


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PDF TMS664414, TMS664814, TMS664164 64M-BIT SMOS69Q
Toshiba Rambus IC

Abstract: CL-GD5462 LG concurrent RDRAM macronix rambus 3d graphics toshiba graphics NEC rdram concurrent 8mb CL-GD546 macronix nintendo LG rambus design
Text: graphics/ video subsystems use multiple DRAMs in 64- bit wide data paths. The Rambus approach to higher , uses only 31 pins on the memory controller, a savings of over 80 pins compared to the 64- bit wide , for systems using 64Mb DRAM technology or 64- bit wide buses, thus providing system manufacturers with , multiple requests to the memory subsystem. At the same time these processors use 64- bit wide internal data , an example, a 64- bit bus operating at 100MHz can demand up to 800 megabytes per second in bandwidth


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PDF 64-MEGABIT 64Mbit 533MHz Toshiba Rambus IC CL-GD5462 LG concurrent RDRAM macronix rambus 3d graphics toshiba graphics NEC rdram concurrent 8mb CL-GD546 macronix nintendo LG rambus design
M5M4V64S20ATP-8A

Abstract: M5M4V64S30ATP-10 M5M4V64S30ATP-8 M5M4V64S30ATP-8A
Text: 4194304-WORD x 4- BIT ) Synchronous DRAM Some of contents are subject to change without notice. The M5M4V64S20ATP is a 4-bank x 4194304-word x 4- bit Synchronous DRAM, with LVTTL interface. All inputs and , M5M4V64S20ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 4194304-WORD x 4- BIT ) Synchronous DRAM DQ0-3 BLOCK DIAGRAM , SDRAM (Rev.1.3) Mar98 M5M4V64S20ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 4194304-WORD x 4- BIT , 64M (4-BANK x 4194304-WORD x 4- BIT ) Synchronous DRAM BASIC FUNCTIONS The M5M4V64S20ATP provides


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PDF Mar98 M5M4V64S20ATP-8A 4194304-WORD M5M4V64S20ATP 125MHz, 125MHz /100MHz M5M4V64S30ATP-10 M5M4V64S30ATP-8 M5M4V64S30ATP-8A
2003 - Not Available

Abstract: No abstract text available
Text: N ew Products MB82DBS02163C MB82DBS04163B Cellular Phone Application Specific Memory 32M- bit / 64M-bit Burst Mode Mobile FCRAMTM MB82DBS02163C/MB82DBS04163B FUJITSU has unveiled a new pair of enhanced 32M- bit and 64M-bit Mobile FCRAMTM devices that adopt burst mode read/write operations in , 64M-bit MB82DBS04163B. Compared to the page mode configured in existing products, the burst mode , Mobile FCRAMs with steadily larger density (increased from 16M- bit to 32M- bit / 64M-bit ), faster speeds


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PDF MB82DBS02163C MB82DBS04163B 32M-bit/64M-bit MB82DBS02163C/MB82DBS04163B 32M-bit 64M-bit MB82DBS04163B.
HY57V16161

Abstract: hy57v168010b 1MX16BIT 4MX16
Text: -139 ·Timing Diagram 64M-bit S D R A M HY57V65401OTC-16Mx4- bit , 4K Ref. 2Bank, 3.3V , - 341 ·Timing Diagram ·SD R A M Device Operation 64M-bit D D R S D R A M HY5DV654023TC , . PRODUCT QUICK REFERENCE S D R A M Fart Numbering Ordering Information 3. DRAM DATA SHEETS 4M- bit S D R A M Page 15 HY57V41610TC- 256Kx16- bit , 1K Ref. 2Bank, 3.3V-· Timing Diagram 16M- bit S D R A M ·B-Gen HY57V16401O B TC -4Mx4- bit , 4K Ref. 2Bank, 3.3V


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PDF HY57V41610TC--------------------- 256Kx16-bit, 16M-bit HY57V16401O --------HY57V168010BTC------------------- -------------------------------HY57V16161 -------------------1Mx16-bit, 64M-bit HY5DV654023TC-------------------- HY57V16161 hy57v168010b 1MX16BIT 4MX16
IS25LQ064

Abstract: IS25LQ
Text: , the status register are not write-protected. When the QE bit of is set "1", the /WP pin (Hardware , by the master device without resetting the serial sequence. When the QE bit of Status Register-2 is , 2 & 3 for Status Register Format and Status Register Bit Definitions. The BP0, BP1, BP2, BP3 and , Status Register bits are described as follows: WIP bit : The Write In Progress (WIP) bit is read-only, and can be used to detect the progress or completion of a program or erase operation. When the WIP bit is


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PDF 64Mbit IS25LQ064 208-mil 16-pin IS25LQ064-JBLE IS25LQ064-JPLE IS25LQ064-JFLE IS25LQ064-JMLE IS25LQ064-JNLI IS25LQ064-JBLI IS25LQ064 IS25LQ
M5M4V64S40ATP-8A

Abstract: No abstract text available
Text: 1048576-WORD x 16- BIT ) Synchronous DRAM Some of contents are subject to change without notice. The M5M4V64S40ATP is a 4-bank x 1048576-word x 16- bit Synchronous DRAM, with LVTTL interface. All inputs and , LSIs SDRAM (Rev.1.3) Mar'98 M5M4V64S40ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 1048576-WORD x 16- BIT , -BANK x 1048576-WORD x 16- BIT ) Synchronous DRAM PIN FUNCTION CLK Input Master Clock: All other , -WORD x 16- BIT ) Synchronous DRAM BASIC FUNCTIONS The M5M4V64S40ATP provides basic functions, bank (row


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PDF M5M4V64S40ATP-8A 1048576-WORD 16-BIT) M5M4V64S40ATP 16-bit 125MHz, 125MHz /100MHz
Not Available

Abstract: No abstract text available
Text: -BANK x 4194304-WQRD x 4- BIT ) Synchronous DRAM PRELIMINARY Some of contents are subject to change , -word x 4- bit Vdd* NC* VddQ « NC * DQ 0« VssQ « NC * NC * VddQ * NC * DQ1 ■V ssQ * NC , Preliminary 64M (4-BANK x 4194304-WORD x 4- BIT ) Synchronous DRAM BLOCK DIAGRAM DQ°-7(°-3> à , (4-BANK x 4194304-WQRD x 4- BIT ) Synchronous DRAM PIN FUNCTION CLK Master Clock: All other , 64M (4-BANK x 4194304-WORD x 4- BIT ) Synchronous DRAM BASIC FUNCTIONS The M5M4V64S20ATP provides


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PDF M5M4V64S20ATP-8, 4194304-WQRD M5M4V64S20ATP 4194304-word 125MHz,
2003 - M6MGD967W33ATP

Abstract: No abstract text available
Text: memory and 32M- bit Mobile RAM in a 52-pin TSOP. 96M- bit Flash memory is constructed by 64M-bit Flash , chip enable2 for upper 64M-bit Flash :Mobile RAM chip enable OE# WE# F-WP# F-RP# M-LB# M-UB , for upper 64M-bit , respectively. It is noted that F-CE1#=F-CE2#="L" is forbidden mode. Note: In this , parametric limits are subject to change. 100,663,296- BIT (6,291,456-WORD BY 16- BIT ) CMOS FLASH MEMORY 33,554,432- BIT (2,097,152-WORD BY 16- BIT ) CMOS Mobile RAM & Stacked- µMCP (micro Multi Chip Package


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PDF M6MGD967W33ATP 296-BIT 456-WORD 16-BIT) 432-BIT 152-WORD M6MGD967W33ATP 96M-bit 32M-bit
8L-10L

Abstract: No abstract text available
Text: SDRAM (Rev.1.3) M ar'98 M5M4V64S30ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 2097152-WORD x 8- BIT , M5M4V64S30ATP is a 4-bank x 2097152-word x 8- bit Synchronous DRAM, with LVTTL interface. All inputs and outputs , '98 M5M4V64S30ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 2097152-WORD x 8- BIT ) Synchronous DRAM DQO-7 MITSUBISHI , '98 M5M4V64S30ATP-8A,-8L,-8, -10L, -10 64M (4-BANK x 2097152-WORD x 8- BIT ) Synchronous DRAM MITSUBISHI LSIs ^ , , -10 64M (4-BANK x 2097152-WORD x 8- BIT ) Synchronous DRAM MITSUBISHI LSIs ^ BASIC FUNCTIONS The


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PDF M5M4V64S30ATP-8A 2097152-WORD M5M4V64S30ATP 125MHz, 8L-10L
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