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ADLINK Technology Inc
NEON-1040 STARTER KIT/SSD32G/64BITS Smart Camera Starter Kit for NEON-1040 ADLINK Smart Camera (Alt: NEON-1040 STARTER KIT/SSD32G/64BITS)
NEON-1040 STARTER KIT/SSD32G/64BITS ECAD Model
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Avnet Americas NEON-1040 STARTER KIT/SSD32G/64BITS 0 1 - - - - - Get Quote

64BITS Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
9240-4i

Abstract: 9261-8i 9240-8i 9260-8i x86 series 9280-4i4e lsi 9260-8i
Text: 9240-8i 9260-4i x86, 64bits 2.6.18.92 , , 64bits 2.6.25-14.fc9 Fedora 12 x86, 64bits 2.6.31.5-127.fc12 Fedora 13 x86, 64bits 2.6.33.3-85 , Debian 5.04 x86, 64bits 2.6.26-2 Debian 5.05 x86, 64bits 2.6.26-2 Mandriva 2009 x86


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PDF 9240xx, 9260xx, 9280xx 9240-4i, 9240-8i, 9260-4i, 9260-8i, 9260DE-8i, 9261-8i, 9280-4i4e 9240-4i 9261-8i 9240-8i 9260-8i x86 series lsi 9260-8i
8708ELP

Abstract: 8704ELP 8708EM2 8888ELP 8880EM2 8704EM2
Text: . MegaRAID Controllers and OS Support Matrix Operating System Architect CentOS 5.2 x86, 64bits , ClearOs 5.2 RC1 x86 Fedora 9 x86, 64bits Fedora 12 x86, 64bits Fedora 13 x86, 64bits FreeBSD 6.3 x86 FreeBSD 7.0 x86 Debian 5.04 x86, 64bits Debian 5.05 x86, 64bits Kernels 8888ELP 8880EM2 2.6.18-194 , .fc9 2.6.26-2 2.6.27-server-0.rc8.2mnb Mandriva 2009 x86, 64bits Mandriva Free 2010 x86, 64bits


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PDF 8704ELP, 8708ELP, 8704EM2, 8708EM2, 8880EM2, 8888ELP. 64bits 8708ELP 8708EM2 8704ELP 8708ELP 8704ELP 8708EM2 8888ELP 8880EM2 8704EM2
2003 - AES-CBC-MAC-128

Abstract: AES-CCM-128 MK72660-01 MK7266 AES-CBC-MAC-32 MLMEScanRequest AES-CCM-32 uAA 180 AXK6F20547YG FIPS-197
Text: when idle Reserved Security capability Allocate address * 64bits Address B0 B1 B2 B3 , DeviceAddress AssocShortAddress 1 3 Status 2 1 4 1 2 U64 64bits Address IEEE , 0x49 No. 1 DeviceAddress U64 64bits Address 2 DisassociateReason U8 , macCoordExtendedAddress 64bits Address ACK 54 MLME-SET.request INVALID_PARAMETER MLME-SET.confirm 1 , descriptor ACLExtendedAddress 64bits Address IEEE Address ACLShortAddress 0x0000­0xFFFF


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PDF FJDK72660 MK72660-01 IEEE802 MK72660-01 250kbps FIPS-197 AES-CBC-MAC-128 AES-CCM-128 MK7266 AES-CBC-MAC-32 MLMEScanRequest AES-CCM-32 uAA 180 AXK6F20547YG
1994 - 32-bit microprocessor architecture

Abstract: MIPS 32-bit bus architecture "64-Bit Microprocessor" 64 bit microprocessor 79R4600 IDT79R4600 R3000 64-BIT
Text: , and arithmetic units are all 64-bits , and the processor directly implements various 64bit operations , path is 64-bits wide. Although not strictly a pre-requisite for a "64-bit processor", the system , , the full register width of the integer and CPU units is used ( 64-bits ); types "int" and "long" are 32 , switch (used with "-mips3") makes all "long" variables and pointers 64-bits , but integers remain 32-bits. - mint64. This switch makes all variables of type "int", "long", and "long long" to be 64-bits , and


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PDF 64-BIT IDT79R4600TM TN-21 R4600 32-bit 32-bits 64bit 32-bit microprocessor architecture MIPS 32-bit bus architecture "64-Bit Microprocessor" 64 bit microprocessor 79R4600 IDT79R4600 R3000
1996 - 79r4600

Abstract: IDT79R4600 R3000 64-BIT
Text: -bit microprocessor; the internal registers, data paths, and arithmetic units are all 64-bits , and the processor , a single cycle; that is, the cache data path is 64-bits wide. Although not strictly a , , the full register width of the integer and CPU units is used ( 64-bits ); types "int" and "long" are 32 , switch (used with "-mips3") makes all "long" variables and pointers 64-bits , but integers remain 32-bits. - mint64. This switch makes all variables of type "int", "long", and "long long" to be 64-bits , and


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PDF 64-BIT IDT79R4600TM TN-21 IDT79 R4600 64-bits, 64bit R4600 32-bit 79r4600 IDT79R4600 R3000
2010 - RT8111

Abstract: No abstract text available
Text: , Win XP 32/ 64-bits , Vista 32/ 64-bits .  Linux 32-bits/ 64-bits and DOS 6.22. Cooling  Two


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PDF FMB-LT35 945GSE 533MHz DDR2-533 GMA950 40-pins 18/24-bits 32/64-bits, RT8111
rk3188

Abstract: RK3188-T ARGB888 emmc boot sequence
Text: ports with 64bits AXI bus interface for system access, AXI bus clock is asynchronous with DDR clock  , Timer „ 7 on-chip 64bits Timers in SoC with interrupt-based operation „ Provide two operation modes , ‹ CPU interconnect with three 64-bits AXI masters, two 64-bits AXI slaves, one 32-bits AHB master and lots of 32-bits AHB/APB slaves ‹ PERI interconnect with two 64-bits AXI masters, one 64-bits AXI , interconnect with six 64-bits AXI masters and one 32-bits AHB slave ‹ GPU interconnect with one 128-bits AXI


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PDF RK3188Technical RK3188 1080p 60fps, 264/MVC/VP8 30fps, RK3188-T ARGB888 emmc boot sequence
2001 - HJ945020

Abstract: M21 M23 d43 309
Text: , 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 6 H'18000000H'1BFFFFFF 8,16,32, 64bits , 32bytes 7*5 [Notes


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PDF HJ945020 SH7750) 64MbSDRAM HM5264165F) M21 M23 d43 309
9698

Abstract: NM6403 ASYNC SRAM
Text: ) Vector operations with 8-bit data up to 3840 MMAC (peak) On-board Memory Power Four 256 K × 64-bits (2 MB) async. SRAM Four 512 K × 64-bits (4 MB) async. SRAM Two 8 M × 64-bits (64 MB) SDRAM


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PDF 64-bit NM6403 9698 NM6403 ASYNC SRAM
2001 - HJ945010

Abstract: hitachi l23
Text: , 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 8,16,32, 64bits , 32bytes 6 H'18000000H'1BFFFFFF 8,16,32, 64bits , 32bytes 7*5 [Notes


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PDF HJ945010 SH7750) 64MbSDRAM HM5264165F) hitachi l23
1N1106

Abstract: LC75822 LC75821 N1106 D106 LC75822E LC75822W 10X10 14X14 SQFP64
Text: OPEN S1 S53, COM1, 2= L : No.4800-3/9 LC75822E, 75822W 1/1duty 64bits , D50 D51 D52 D53 DP 0 0 A3 1/2duty 52 64bits 1/1duty D54 D106 128bits 0 1 , ILC03524 No.4800-4/9 LC75822E, 75822W 1/1duty 64bits CE tcp tcs tch CL tøH tøL 0


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PDF LC75822E, 5822W N4800C LC75822W LC75822 LC75821 CR10--5s 1N1106 LC75822 LC75821 N1106 D106 LC75822E LC75822W 10X10 14X14 SQFP64
1999 - AP-909

Abstract: processor 8086 flags processor pentium GenuineIntel ap909 119H INTEL application notes Intel486TM PROCESSOR FAMILY Intel AP
Text: lower 64-bits of 96-bit processor serial number 4 EAX highest value Intel Reserved EAX , Parameters EBX Configuration Parameters EDX ECX Output of CPUID if EAX = 3 31 Lower 64-bits of 96-bit processor serial number 0 EDX Upper 32-bits (of Lower 64-bits ) ECX Lower 32-bits (of Lower 64-bits ) 000959 Figure 2. CPUID Instruction Outputs 7 E f f e d s a P 3.1. Presence , value in EAX should be saved prior to gathering the remaining 64-bits of the processor serial number


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PDF AP-909 USA/96/POD/PMG AP-909 processor 8086 flags processor pentium GenuineIntel ap909 119H INTEL application notes Intel486TM PROCESSOR FAMILY Intel AP
3x4 KEYPAD

Abstract: wiegand code el300 Wiegand EL3102 keypad 3x4 elko switch EM4100 wiegand output 26-bits
Text: tags( 64Bits ,Manchester coding) · Support 3x4 keypad for password input · Built-in bi-color LED and , format EL300-2/310-2 reader support EM4100 or compatible 64bits read only tags with Manchester Coding


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PDF 05-10V1 EL300-2 EL310-2 EL300-2/310-2 EM4100 150mm 100ms 26bits 64Bits 3x4 KEYPAD wiegand code el300 Wiegand EL3102 keypad 3x4 elko switch wiegand output 26-bits
x86 addressing mode

Abstract: 32-bit microprocessor architecture intel x86 processor architecture x86 processor architecture intel x86-64 gprs abstract interrupts of x86 microprocessor how to define amd athlon 64 app abstract
Text: user's timeframe. Forces the costly transition of many 32-bit applications that do not require 64-bits , this encoding, default operand size is 32-bits and default address size is 64-bits . Using instruction prefixes, the default operand size can be overridden to 64-bits or 16-bits, and the default address size , with single code, data, and stack space. The default address size is 64-bits , and the default , are addressed as RAX In 64-bit Mode, General Purpose Registers (GPRs) are extended to 64-bits . The


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PDF X86-64TM 64-bit x86-64 x86 addressing mode 32-bit microprocessor architecture intel x86 processor architecture x86 processor architecture intel x86-64 gprs abstract interrupts of x86 microprocessor how to define amd athlon 64 app abstract
2009 - Not Available

Abstract: No abstract text available
Text: operativo XP de 64-bits o Windows Servidor 2003 de 32-bits, inicie la instalación desde la siguiente , ordenador utiliza el sistema operativo Vista 64-bits , Windows 2008 o Windows 7 siga el procedimiento


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PDF
1997 - 200H

Abstract: MSP430 0134H 0138H 013AH 0132H 16x16-bit 16x16bit
Text: * * EXAMPLE TO ADD THE RESULT OF THE HARDWARE MULTIPLICATION * * TO THE RAM DATA, 64BITS , * * EXAMPLE TO ADD THE RESULT OF THE HARDWARE MULTIPLICATION * * TO THE RAM DATA, 64BITS , THE RESULT OF THE HARDWARE MULTIPLICATION * * TO THE RAM DATA, 64BITS * * THE RESULT OF THE , * * EXAMPLE TO ADD THE RESULT OF THE HARDWARE MULTIPLICATION * * TO THE RAM DATA, 64BITS


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PDF MSP430 MSP43bling 200H 0134H 0138H 013AH 0132H 16x16-bit 16x16bit
1997 - XC4000

Abstract: XC4000XL XC4052XL
Text: frequency measurements to be taken. High Freq. 2 Logic Levels 64-bits /32-bits 4-bit/1 level Medium Freq. 4 Logic Levels 64-bits /8-bits 16-bit/1 level Low Freq. 8 Logic Levels 64-bits /1-bit 64


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PDF XC4000XL-1 100MHz XC4000XL XC4062XL-1 10K100-3 XC4000XL-1 XC4052XL. XC4000 XC4052XL
1998 - ADSP-21060 reference manual

Abstract: Frequency multiplier 100MHz ADSP-21160 interrupt Assembly sharc sharc ADSP-2106x architecture 4 bit barrel shifter 4 bit barrel shifter circuit diagram ADSP-21000 ADSP-21060 register pairs in ADSP-21060
Text: Enhancements: Enhanced support for synchronous interfacing Data bus width increased to 64-bits (synchronous , capability as DAG1. The DAG registers can be read/written in pairs, moving 64-bits /cycle. Additionally, the , The host interface can take advantage of the data bus width increase to 64-bits . The asynchronous , to: shared data bus width increase to 64-bits new shared bus transfer protocols shared bus


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PDF ADSP-21160 32-bit ADSP-21000 ADSP-160 ADSP-21160s ADSP-21060 reference manual Frequency multiplier 100MHz interrupt Assembly sharc sharc ADSP-2106x architecture 4 bit barrel shifter 4 bit barrel shifter circuit diagram ADSP-21060 register pairs in ADSP-21060
NL82721

Abstract: NL82721R NLM82721R-25 NLM82721R-33 Ternary CAM "routing tables"
Text: -bit enable pin (ULEN) allows access to either the upper 64-bits or the lower 64-bits of the 128-bit words , upper 64-bits or the lower 64-bits of the 128-bit memory, Global Mask, Comparand, and Status Register , 64-bits wide. In NL82721R device, the external interface is 64-bit wide and the internal words are , interfacing IPCAM-1R Module to buses smaller than 64-bits wide. In NL82721R device, the external interface , local mask word at address from the Address Counter (ACR) the first 64-bits (ULEN=1). Write to local


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PDF NLM8x721R NLM8x721R NL82721R NL82721 NLM82721R-25 NLM82721R-33 Ternary CAM "routing tables"
nfa 102

Abstract: ipCAM ethernet module ternary content addressable memory NL82721 NL82721R NLM82721R-25 NLM82721R-33 ipCAM 8Kx128 Ternary CAM
Text: pin (ULEN) allows access to either the upper 64-bits or the lower 64-bits of the 128-bit words of , enables access to the upper 64-bits or the lower 64-bits of the 128-bit memory, Global Mask, Comparand , restrictions should be kept in mind when interfacing the IPCAM-1R Module to buses smaller than 64-bits wide , IPCAM-1R Module to buses smaller than 64-bits wide. In NL82721R device, the external interface is 64 , ) the first 64-bits (ULEN=1). Write to local mask word at address from ACR the second 64-bits (ULEN


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PDF NLM8x721R NLM8x721R NL82721R nfa 102 ipCAM ethernet module ternary content addressable memory NL82721 NLM82721R-25 NLM82721R-33 ipCAM 8Kx128 Ternary CAM
1995 - R4640

Abstract: R4650 IDTR4640 R4000 R4700 mips r4700
Text: MICROPROCESSOR IDT R4640 Offers Superior Price/Performance for 64-Bits The R4640 microprocessor is an IDT , delivers the high performance of 64-bits at 32-bit prices for internetworking, office automation, and


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PDF ORIONTMR4640TM R4640TM R4640 R4650 IDTR4640 R4000 R4700 mips r4700
2001 - new 7901

Abstract: 8165-PB5 8065PB5 hifn 8154
Text: 1962 ­ Compression Control Protocol 64-bits 66-MHz PCI Bus 32 or 64-bits RFC 1967 ­ PPP


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PDF OC-12 Plus76-TBGA 8165-PB5 8065-PB5 576-TBGA new 7901 8165-PB5 8065PB5 hifn 8154
msc251

Abstract: msc250 MSC-251
Text: 72kbits) Contact synchronous ROM (MAX 256kbits) High density multiplier compiler (MAX 64bits X 64bits


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PDF MSC250/251 MSC250/251 25-micron msc251 msc250 MSC-251
FIPS46-3

Abstract: microcontroller in medical APPLICATION nec control code
Text: 64-bits and can be used with any 78K0R/Kx3-L ,/IX3 ,/LX3 or /FX3 family microcontroller , initializes the keys that will be used to encrypt or decrypt the messages; you just need to pass the key ( 64-bits


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PDF 78K0R 16-Bit U19669EE1V0AN00 32-bit FIPS46-3 microcontroller in medical APPLICATION nec control code
HEF4557BD

Abstract: HEF4557B LSI HEF4557BT HEF4557B HEF4557BP D102I HEF4557BPN HEF4557 NSL-32
Text: , independent of the other inputs. 9 3 12 13 14 15 1 MR -32 ■16 -8 -1 SHIFT REGISTER 64-BITS Fig. 1 Functional , H H H H H H H H H H L H L H 61-bits 62-bits 63-bits 64-bits A.C. CHARACTERISTICS Vgs = 0 V; Tgrni


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PDF HEF4557B 1-to-64 HEF4557BD HEF4557B LSI HEF4557BT HEF4557BP D102I HEF4557BPN HEF4557 NSL-32
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