6 INPUTS OR GATE TRUTH TABLE Search Results

Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED A Add figure 3. Change tPHL and footnotes in table I. Editorial changes throughout. 88-04-04 M. A. Frye B Changes in accordance with NOR 5962-R240-92. 92-07-10 Monica Poelking C Changes in accordance with NOR 5962-R026-93.

PAL20L10AMJS

Abstract: PAL20L8AMJS PAL20X8AMJS 8412906LA 8412909 PAL20X10AMJS TIBPAL20L10-25MJTB 8412909LA PAL20R4A-2MJS/883B PAL20R8AMJ
Contextual Info: REVISIONS LTR C D E DESCRIPTION DATE YR-MO-DA Convert to military drawing format. Add vendor CAGE 01295. Changes to table I. Delete subgroup 9 from final electrical test parameters. Add case outline X. Added four devices 09 - 12. Update part numbers for vendor CAGE number 01295. Correction on

S9301

Abstract: S-9301 74195 pin configuration 74195 pin diagram N9300B HA2E 74195 function table N9301
Contextual Info: SPEED/PACKAQE AVAILABILITY 54LS F,W FUNCTION TABLE PIN CONFIGURATION EACH GATE 74LS A INPUTS A B L L H H L H L H OUTPUT L H H L H = high level L = low level SWITCHING CHARACTERISTICS PARAMETER* *PLH *PHL 'PLH *PHL FROM (INPUT) Vc c = 5V, TA = 25"C LIMITS

qml-38535

Abstract: 77024-01 CDFP2-F14 DIMENSIONS
Contextual Info: REVISIONS LTR DESCRIPTION DATE YR-MO-DA APPROVED D Convert to SMD format. Added device type 02. Technical changes to 1.3, 1.4, Table I and Table II. Editorial changes throughout. 92-01-23 Monica L. Poelking E Update boilerplate to MIL-PRF-38535 requirements. - jak

E0600

Abstract: MACH210 P16H8 binary to bcd decoder 4 digit COUNTER LED bcd 7449 BCD to 7-segment 7449 decoder and seven segment display 7449 7-segment decoder logic diagram IF-6-24 EP600
Contextual Info: ABEL-HDL Reference Table of Contents 1. Introduction 2. Language Structure Summary . . . . . . . . . . . . . . . . . . . . Introduction to ABEL-HDL . . . . . . . . . . Basic Syntax . . . . . . . . . . . . . . . . . . Supported ASCII Characters . . . . . . .

binary to bcd decoder

Abstract: LT 543 7-segment display PAL Decoder 16L8 MACH210 P16R4 P22V10 EP600 P16V8S 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION diagram ABEL-HDL Reference Manual
Contextual Info: ABEL-HDL Reference Table of Contents 1. Introduction 2. Language Structure Summary . . . . . . . . . . . . . . . . . . . . Introduction to ABEL-HDL . . . . . . . . . . Basic Syntax . . . . . . . . . . . . . . . . . . Supported ASCII Characters . . . . . . .

SN74LS47N PIN DIAGRAM

Abstract: IC TTL 7400 diagram and truth table 74lsxxx data sheet 74 LS147 pin configuration layout INTERNAL STRUCTURE LS156 SN74LS47N pin configuration DL121 IC 7400 diagram and truth table philips semiconductor data handbook sn74ls47n counter
Contextual Info: DL121/D Rev. 6, Jan-2000 ON Semiconductor LS TTL Data ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC SCILLC . SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does

T74LS266B1

Abstract: n70v T54LS266D2 T74LS266
Contextual Info: ses T§|LjS206 TMS286 QUAD 2-INPUT EXCLUSIVE NOR GATE DESCRIPTION The T54LS266/T74LS266 is a high speed QUAD 2-INPUT EXCLUSIVE NOR GATE with open col­ lector output fabricated in LOW POWER SCHOTTKY technology. 1 1 B1 Plastic Package D1/D2 Ceramic Package

HD1-4702-9

Abstract: hd-4702-9 f 4702 5962-9051801MEA 93L34 HD3-4702-9 HD-4702 RS-404 hd347
Contextual Info: HD-4702 TM CMOS Programmable Bit Rate Generator March 1997 Features Description • HD-4702 Provides 13 Commonly Used Bit Rates The HD-4702 Bit Rate Generator provides the necessary clock signals for digital data transmission systems, such as a UART. It generates 13 commonly used bit rates using an on-chip crystal

Contextual Info: Freescale Semiconductor, Inc. MOTOROLA Document order number: MPC17531A Rev 1.0, 04/2004 SEMICONDUCTOR TECHNICAL DATA Advance Information 17531A 700 mA Dual H-Bridge Motor Driver with 3.0 V Compatible Logic I/O 3.0 V LOGIC COMPATIBLE 700 mA DUAL H-BRIDGE MOTOR DRIVER IC

Contextual Info: u m TECHNOLOGY Final Electrical Specifications LTC1470 Single PCMCIA Protected 5V/3.3V VCc Switch N o v e m b e r 1994 KOTURCS DCSCRIPTIOn • 3.3V/5V Switching in 8-Pin SOIC Package ■ Built-In Current Limit and Thermal Shutdown ■ Extremely Low Rds on MOSFET Switches

74LCX86

Abstract: 74LCX86M 74LCX86MTR 74LCX86TTR TSSOP14
Contextual Info: 74LCX86 LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED : tPD = 6.5ns MAX. at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V

74LCX02

Abstract: 74LCX02M 74LCX02MTR 74LCX02TTR TSSOP14
Contextual Info: 74LCX02 LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED : tPD = 4.4ns MAX. at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V

74LCX00

Abstract: 74LCX00M 74LCX00MTR 74LCX00TTR TSSOP14
Contextual Info: 74LCX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ 5V TOLERANT INPUTS HIGH SPEED : tPD = 4.3ns MAX. at VCC = 3V POWER DOWN PROTECTION ON INPUTS AND OUTPUTS SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 24mA (MIN) at VCC = 3V

74LVX132

Abstract: 74LVX00 74LVX132M 74LVX132MTR 74LVX132TTR TSSOP14
Contextual Info: 74LVX132 LOW VOLTAGE CMOS QUAD 2-INPUT SCHMITT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 5.9ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C TYPICAL HYSTERESIS : 0.7V at VCC = 3.3V

ttl 74ls10

Abstract: truth table NOT gate 74 74LS10 74LS10 truth table 751A-02 SN54-74LS10 74LS10 TTL 3 input nand gate 74LS10
Contextual Info: SN54/74LS10 TRIPLE 3-INPUT NAND GATE TRIPLE 3-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

truth table 74ls54

Abstract: 4 inputs OR gate truth table 751A-02 74Ls54 SN74LSXXD SN54LSXXJ SN74LSXXN truth table NOT gate 74 3-2-2-3-input AND-OR-invert gate
Contextual Info: SN54/74LS54 3-2-2-3-INPUT AND-OR-INVERT GATE 3-2-2-3-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 1 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

74LVX86

Abstract: 74LVX86M 74LVX86MTR 74LVX86TTR TSSOP14
Contextual Info: 74LVX86 LOW VOLTAGE CMOS QUAD EXCLUSIVE OR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 5.8 ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX27

Abstract: 74LVX27M 74LVX27MTR 74LVX27TTR TSSOP14
Contextual Info: 74LVX27 LOW VOLTAGE CMOS TRIPLE 3-INPUT NOR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVX32

Abstract: 74LVX32M 74LVX32MTR 74LVX32TTR TSSOP14
Contextual Info: 74LVX32 LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.4ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V AT VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVQ86

Abstract: 74LVQ86M 74LVQ86MTR 74LVQ86TTR TSSOP14
Contextual Info: 74LVQ86 QUAD EXCLUSIVE OR GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.5ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V 75Ω TRANSMISSION LINE DRIVING

74LVQ32

Abstract: 74LVQ32M 74LVQ32MTR 74LVQ32TTR TSSOP14
Contextual Info: 74LVQ32 LOW VOLTAGE CMOS QUAD 2-INPUT OR GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5.2 ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA (MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V

74LVX00

Abstract: 74LVX00M 74LVX00MTR 74LVX00TTR TSSOP14
Contextual Info: 74LVX00 LOW VOLTAGE CMOS QUAD 2-INPUT NAND GATE WITH 5V TOLERANT INPUTS • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED : tPD = 4.1ns TYP. at VCC = 3.3V 5V TOLERANT INPUTS INPUT VOLTAGE LEVEL : VIL=0.8V, VIH=2V at VCC=3V LOW POWER DISSIPATION: ICC = 2 µA (MAX.) at TA=25°C

74LVQ02

Abstract: 74LVQ02M 74LVQ02MTR 74LVQ02TTR TSSOP14
Contextual Info: 74LVQ02 LOW VOLTAGE CMOS QUAD 2-INPUT NOR GATE • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 5 ns TYP. at VCC = 3.3 V COMPATIBLE WITH TTL OUTPUTS LOW POWER DISSIPATION: ICC = 2µA(MAX.) at TA=25°C LOW NOISE: VOLP = 0.3V (TYP.) at VCC = 3.3V