6 INPUTS OR GATE Search Results

Contextual Info: SIÏlsC MON35W82 STANDARD MICROSYSTEMS CORPORATION Hardware Monitoring IC - l2C Interface Only FEATURES Monitoring Items 3 Thermal Inputs From Remote Thermistors or 2N3904 NPN-type Transistors or Pentium II Deschutes thermal diode output 6 Voltage Inputs

48h diode zener

Abstract: 2N3904 MON35W42 MON35W82
Contextual Info: MON35W82 Hardware Monitoring IC – I2C Interface Only FEATURES • • Monitoring Items 3 Thermal Inputs From Remote Thermistors or 2N3904 NPN-type Transistors or PentiumTM II Deschutes thermal diode output 6 Voltage Inputs Typical for Vcore, +3.3V, +12V,

Contextual Info: 74HC2G32; 74HCT2G32 Dual 2-input OR gate Rev. 5 — 6 January 2014 Product data sheet 1. General description The 74HC2G32; 74HCT2G32 is a dual 2-input OR gate. Inputs include clamp diodes. This enables the use of current limiting resistors to interface inputs to voltages in excess of

Contextual Info: MON35WÔ2 SlllgC STANDARD MICROSYSTEMS CORPORATION Hardware Monitoring 1C - l2C Interface Only FEATURES • • M onitoring Items 3 Thermal Inputs From Remote Therm istors or 2N3904 NPN-type Transistors or Pentium II Deschutes thermal diode output 6 Voltage Inputs

Contextual Info: 74HC2G32-Q100; 74HCT2G32-Q100 Dual 2-input OR gate Rev. 2 — 6 January 2014 Product data sheet 1. General description The 74HC2G32-Q100; 74HCT2G32-Q100 is a dual 2-input OR gate. Inputs include clamp diodes that enable the use of current limiting resistors to interface inputs to voltages in

SRQ10

Contextual Info: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER D3644. OCTOBER 1990-R EV ISE D APRIL1993 DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs 1 2 3 4 5 6 7 qf [ 8

54HC165

Abstract: 4HC165
Contextual Info: SN54HC165, SN74HC165 PARALLEL LOAD 8-BIT SHIFT REGISTERS D2684. DECEMBER 1982-REVISED SEPTEMBER 1987 Complementary Outputs S N 5 4 H C 1 6 5 . . . J PACKAGE S N 7 4 H C 1 6 5 . . . D OR N PACKAGE Direct Overriding Load Data Inputs (TOP VIEW } Gated Clock Inputs

AC86

Abstract: ti AC86 SN54AC86 SN74AC86 SN74AC86D SN74AC86DBR SN74AC86DR SN74AC86N SN74AC86NSR SN74AC86PWR
Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533B – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V

Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533B – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V

Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533B – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V

LS164

Abstract: SN54ALS164 TE 2162
Contextual Info: PRODUCT PREVIEW SN 54A LS164, SN 74 A LS1 64 8-BIT PARALLEL OUT SERIAL SHIFT REGISTERS 0 2 6 6 1 . A P R IL 1 9 8 2 - R E V IS E D M A Y 1 9 8 6 SN54ALS164 . . . J PACKAGE SN74ALS164 . . . D OR N PACKAGE • AND-Gated Enable/Disable Serial inputs • Fully Buffered Clock and Serial Inputs

54164

Abstract: IC 74164
Contextual Info: SN54164, SN 54LS164, SN74164, S N 74LS164 8-BIT PARALLEL-OUT SERIAL SHIFT REGISTERS MAR C H 1 9 7 4 - REVISED M AR C H 1988 Gated Serial Inputs S N 5 4 1 6 4 , S N 54 L S 1 6 4 . . . J OR W PACKAGE • Fully Buffered Clock and Serial Inputs S N 7 4 1 6 4 . . . N PACKAGE

Contextual Info: ZL40221 Precision 2:6 LVDS Fanout Buffer with Glitchfree Input Reference Switching and On-Chip Input Termination Data Sheet April 2014 Features Ordering Information ZL40221LDG1 ZL40221LDF1 Inputs/Outputs • Accepts two differential or single-ended inputs

Contextual Info: ZL40221 Precision 2:6 LVDS Fanout Buffer with Glitchfree Input Reference Switching and On-Chip Input Termination Data Sheet February 2013 Features Ordering Information ZL40221LDG1 ZL40221LDF1 Inputs/Outputs • Accepts two differential or single-ended inputs

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Quad 2 -In p u t OR G ate w ith LSTTL-C om patible Inputs M C54/74HCT32A High-Performance Silicon-Gate CMOS J SUFFIX CERAM IC PACKAGE CASE 6 3 2 -0 8 The MC54/74HCT32A may be used as a level converter for interfacing TTL or NMOS outputs to H igh-S peed CMOS inputs.

Contextual Info: SN54HC165, SN74HC16S PARALLEL LOAD 8 BIT SHIFT REGISTERS D 26B 4, DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 Complementary Outputs S N 5 4 H C 1 6 6 - . J P AC KA G E SN 74H C 165 D OR N P AC KAG E • Direct Overriding Load Data Inputs • Gated Clock Inputs

JESD22-C101E

Contextual Info: 74LVC00A Quad 2-input NAND gate Rev. 6 — 6 January 2012 Product data sheet 1. General description The 74LVC00A provides four 2-input NAND gates. Schmitt trigger action at all inputs makes the circuit tolerant of slower input rise and fall times. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these

Contextual Info: SN54AC10, SN74AC10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE

Contextual Info: SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS529C – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE

Contextual Info: SN54AC11, SN74AC11 TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCAS532D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 7.5 ns at 5 V SN54AC11 . . . J OR W PACKAGE SN74AC11 . . . D, DB, N, NS, OR PW PACKAGE

Contextual Info: SN54AC10, SN74AC10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE

Contextual Info: SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCAS529C – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE

Contextual Info: SN54AC10, SN74AC10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE

SN54AC10

Abstract: SN74AC10 SN74AC10D SN74AC10DBR SN74AC10DR SN74AC10N SN74AC10NSR SN74AC10PW SN74AC10PWR
Contextual Info: SN54AC10, SN74AC10 TRIPLE 3ĆINPUT POSITIVEĆNAND GATES SCAS529D − AUGUST 1995 − REVISED OCTOBER 2003 D 2-V to 6-V VCC Operation D Inputs Accept Voltages to 6 V D Max tpd of 6.5 ns at 5 V SN54AC10 . . . J OR W PACKAGE SN74AC10 . . . D, DB, N, NS, OR PW PACKAGE