6 INPUT OR GATE Search Results

TC7MP01FK

Contextual Info: TC7MP01FK TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC7MP01FK Low-Voltage Triple Gate 6-input AND + 4-input OR + inverter The TC7MP01FK is a high-performance CMOS triple gate (6-input AND + 4-input OR + inverter). Desinged for use in 1.8 V, 2.5 V, or 3.3 V systems, it achieves high-speed operation

74hct386

Contextual Info: GD54/74HC386, GD54/74HCT386 QUAD 2-INPUT EXCLUSIVE OR GATES General Description These devices are identical in pinout to the 5 4 /7 4 L S 3 8 6 . They contain four independent 2-input Exclusive OR gates. The HC/HCT 3 8 6 are electrically identical to the HC/HCT 8 6 , However,

SN54136

Abstract: SDLS048 LS136 SN54LS136 SN74136 SN74LS136
Contextual Info: SN54136, SN54LS136, SN74136, SN74LS136 QUADRUPLE 2-INPUT EXCLUSIVE OR GATES WITH OPEN-COLLECTOR OUTPUTS SDLS048 DECEMBER 1972 - REVISED MARCH 1988 S N 5 4 1 3 6 , S N 5 4 L S 1 3 6 . , . J OR W PACKAGE S N 7 4 1 3 6 . . . N PACKAGE S N 74LS 13 6 . . . D OR N PACKAGE

ic 74LS266

Contextual Info: SN54LS266, SN74LS266 QUADRUPLE 2-INPUT EXCLUSIVE NOR GATES WITH OPEN COLLECTORS OUTPUTS DECEMBER 1972 - REVISED MARCH 1988 • Can Be Used as a 4-Bit Digital Comparator SN 5 4 L S 2 6 6 . . . J OR W PACKAG E SN 7 4LS2 66 . . . D OR N PACKAG E Input Clamping Diodes Simplify System

74LVQ86

Abstract: 74LVQ86SC 74LVQ86SCX 74LVQ86SJ 74LVQ86SJX M14A
Contextual Info: LVQ86 National Semiconductor 74LVQ86 Low Voltage Quad 2-Input Exclusive-OR Gate General Description Features The LVQ8 6 contains four, 2-input exclusive-OR gates. • Ideal for low power/low noise 3.3V applications ■ Guaranteed simultaneous switching noise level and

74HC1G32GW

Abstract: 74HC1G32 74HC 74HC1G32GV 74HC32 74HCT1G32 74HCT1G32GV 74HCT1G32GW 74HCT32
Contextual Info: 74HC1G32; 74HCT1G32 2-input OR gate Rev. 05 — 14 March 2008 Product data sheet 1. General description 74HC1G32 and 74HCT1G32 are high-speed Si-gate CMOS devices. They provide a 2-input OR function. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

VM MARKING CODE SOT353

Abstract: hct1g32
Contextual Info: 74HC1G32; 74HCT1G32 2-input OR gate Rev. 04 — 14 May 2007 Product data sheet 1. General description 74HC1G32 and 74HCT1G32 are high-speed Si-gate CMOS devices. They provide a 2-input OR function. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

74HC2G32

Abstract: 74HC2G32DC 74HC2G32DP 74HCT2G32 74HCT2G32DC 74HCT2G32DP JESD22-A114E
Contextual Info: 74HC2G32; 74HCT2G32 Dual 2-input OR gate Rev. 03 — 12 May 2009 Product data sheet 1. General description The 74HC2G32 and 74HCT2G32 are high-speed Si-gate CMOS devices. They provide two 2-input OR gates. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

74HC

Abstract: 74HC1G86 74HC1G86GV 74HC1G86GW 74HCT1G86 74HCT1G86GV 74HCT1G86GW
Contextual Info: 74HC1G86; 74HCT1G86 2-input EXCLUSIVE-OR gate Rev. 04 — 20 July 2007 Product data sheet 1. General description 74HC1G86 and 74HCT1G86 are high-speed Si-gate CMOS devices. They provide a 2-input EXCLUSIVE-OR function. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA MC10E101 M C100E101 • 500 ps Max. Propagation Delay • Extended 100E Vgg Range o f - 4 .2 V to -5 .4 6 V • 75 k il Input P ulldow n Resistors The MC10E/100E101 Is a quad 4-input OR/NOR gate. QUAD 4-INPUT OR/NOR GATE

hct nxp

Abstract: 74HCT2G86DC 74HCT2G86DP JESD22-A114E 74HC2G86 74HC2G86DC 74HC2G86DP 74HCT2G86
Contextual Info: 74HC2G86; 74HCT2G86 Dual 2-input exclusive-OR gate Rev. 03 — 7 May 2009 Product data sheet 1. General description The 74HC2G86 and 74HCT2G86 are high-speed Si-gate CMOS devices. They provide two 2-input exclusive-OR gates. The HC device has CMOS input switching levels and supply voltage range 2 V to 6 V.

Contextual Info: 74AUP2G32 Low-power dual 2-input OR gate Rev. 5 — 6 December 2011 Product data sheet 1. General description The 74AUP2G32 provides dual 2-input OR function. Schmitt-trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP2G32 Low-power dual 2-input OR gate Rev. 6 — 5 June 2012 Product data sheet 1. General description The 74AUP2G32 provides dual 2-input OR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: 74AUP2G32 Low-power dual 2-input OR gate Rev. 6 — 5 June 2012 Product data sheet 1. General description The 74AUP2G32 provides dual 2-input OR function. Schmitt trigger action at all inputs makes the circuit tolerant to slower input rise and fall times across the entire VCC range from 0.8 V to 3.6 V.

Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533B – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V

Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533B – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V

AC86

Abstract: ti AC86 SN54AC86 SN74AC86 SN74AC86D SN74AC86DBR SN74AC86DR SN74AC86N SN74AC86NSR SN74AC86PWR
Contextual Info: SN54AC86, SN74AC86 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES SCAS533B – AUGUST 1995 – REVISED SEPTEMBER 2002 D D D SN54AC86 . . . J OR W PACKAGE SN74AC86 . . . D, DB, N, NS, OR PW PACKAGE TOP VIEW 2-V to 6-V VCC Operation Inputs Accept Voltages to 6 V Max tpd of 9 ns at 5 V

74LVC2G32

Abstract: 74LVC2G32DC 74LVC2G32DP 74LVC2G32GM 74LVC2G32GT JESD22-A114E MO-187
Contextual Info: 74LVC2G32 Dual 2-input OR gate Rev. 07 — 6 June 2008 Product data sheet 1. General description The 74LVC2G32 provides a 2-input OR gate function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in a mixed 3.3 V and 5 V environment.

Contextual Info: 74LVC1G32 Single 2-input OR gate Rev. 8 — 6 December 2011 Product data sheet 1. General description The 74LVC1G32 provides one 2-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

Contextual Info: 74LVC1G332 Single 3-input OR gate Rev. 4 — 6 December 2011 Product data sheet 1. General description The 74LVC1G332 provides one 3-input OR function. Inputs can be driven from either 3.3 V or 5 V devices. This feature allows the use of these devices as translators in mixed 3.3 V and 5 V applications.

74LS51 truth table

Abstract: 74ls51 4 inputs OR gate truth table truth table SN54LSXXJ SN74LSXXN SN74LSXXD truth table NOT gate 74 751A-02
Contextual Info: SN54/74LS51 DUAL 2-WIDE 2-INPUT/ 3-INPUT AND-OR-INVERT GATE DUAL 2-WIDE 2-INPUT/ 3-INPUT AND-OR-INVERT GATE LOW POWER SCHOTTKY VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 14 1 2 3 4 5 6 1 7 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02

20-PIN

Abstract: 50J2 M74LS386P
Contextual Info: MITSUBISHI LSTTLs M74LS386P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATE DESCRIPTION The M 7 4 L S 3 8 6 P is a semiconductor circuit containing four integral circuits configured into dual input exclusive OR gates. FEATURES • Capable o f withstanding high input voltages V , ^ 1 5 V

74LS386P

Contextual Info: MITSUBISHI LSTTLs M74LS386P QUADRUPLE 2-IN P U T EXCLUSIVE OR GATE DESCRIPTION The M 7 4 L S 3 8 6 P is a semiconductor circuit containing four integral circuits configured into dual input exclusive OR gates. FEATURES • Capable o f withstanding high input voltages V , ^ 1 5 V

104050

Abstract: hef4075bp
Contextual Info: HEF4075B gates TRIPLE 3-INPUT OR GATE The HEF4075B provides the positive trip le 3-input OR function. The outputs are fu lly buffered for highest noise im m unity and pattern insensitivity o f o u tp u t impedance. Vqo Ig D la I7 O3 O2 ^6 HEF4075B TininirwTEninzr