54ACT Search Results

2SC 2320

Abstract: SCAS04QA-P3110
Contextual Info: 54ACT11253,74ACT11253 DUAL 1-0F-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS040A - D3110, MARCH 1988 - REVISED APRIL 1993 * Inputs Are TTL-Voltage Compatible 54ACT11253 . . . J PACKAGE 74ACT11253 . . . D OH N PACKAGE TOP VIEW * 3-State Version of'ACT11153

Contextual Info: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS S C A S Q 2 3 A - D2957, JU L Y 1978- R E V IS E D A P R I L 1993 54ACT11521 . . . J P A C K A G E 74ACT11521 . . . OB, D W O R N P A C K A G E i * Compares Two 8-Bit Words * Inputs Are TTL-Voltage Compatible

Contextual Info: 54ACT11002,74ACT11002 QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS003A - D2957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-PIn V^c and GND Configurations Minimize High-Speed Switching Noise

1sv 134

Contextual Info: 54ACT11640, 74ACT11640 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTS SCAS027A - D2957, JULY 1987 - REVISED APRIL 1993 54ACT11640. . . JT PACKAGE 74ACT11640 . . . DW OR NT PACKAGE TOP VIEW B idirectional Bus Transceivers In H ig h-D ensity 24-P in Packages

Contextual Info: 54ACT11652, 74ACT11652 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0123— D3106, DECEMBER 1989 5 4 A C T 11 6 52 . . . J T PACKA GE • Inputs are TTL-Voltage Compatible 7 4 A C T 1 1652 . . . D W OR N T P ACKA G E • Bus Transceivers/Registers

TI0149-D3373

Contextual Info: 54ACT11827, 74ACT11827 10-BIT BUFFERS/BUS DRIVERS WITH 3-STATE OUTPUTS TI0149— D3373, NOVEM BER 19B9— REVISED MARCH 1990 54ACT11827 . . . JT PACKAGE 74ACT11827 . . . DW OR NT PACKAGE • Inputs are TTL-Voltage Compatible 3-State Outputs Drive Bus Lines or Buffer

tl401

Contextual Info: 54ACT11074, 74ACT11074 DUAL D-TYPE POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET _ SCAS046 - D2957. DECEMBER 1986 - REVISED APRIL 1993 54ACT11074. . . J PACKAGE 74ACT11074. . . D OR N PACKAGE * Inputs Are TTL-Voltage Compatible

Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout

Contextual Info: 54ACT11241, 74ACT11241 OCTAL BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS T I0073— D2957 JULY 1987— REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 54A C T 11241 . . . J T P ACKA G E 74A C T11 2 41 . . . D W OH N T P ACKA G E • 3-State Outputs Drive Bus Lines or Buffer

Contextual Info: 54ACT11874, 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D3447, MAR CH 1990-R E V IS E D O C TO BER 1990 54A C T 11 8 74 . . . J T P A C K A G E Inputs are TTL-Voltage C om patible 74A C T 11 8 74 . . . D W O R N T P A C K A G E

D2957

Abstract: 1987-REVISEDAPRIL
Contextual Info: 54ACT11030,74ACT11030 8-INPUT POSITIVE-NAND GATES _ D2957. MARCH 1987-REVISEDAPRIL 1993 Inputs Are TTL*Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GNO Configurations Minimize High-Speed Switching Noise EPIC Enhanced-Perlormance Implanted

ti0041

Contextual Info: 54ACT11000, 74ACT11000 QUADRUPLE 2-INPUT POSITIVE-NAND GATES T I0041— D2957, JUNE 1967— REVISED M ARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 00 . . . J P ACKA G E 7 4 A C T 1 1000 . . . D O R N PACKA GE • Flow-Through Architecture to Optimize PCB

Contextual Info: 54ACT16543, 74ACT16543 16-BIT REGISTERED TRANSCEIVERS WITH 3-STATE OUTPUTS TI0194— D3476, MARCH 1990 Members of the Texas Instruments Widebus Family S4ACT16543 . . . WD PACKAGE 74ACT16S43 . . . DL PACKAGE TOP VIEW Packaged in Shrink Small-Outline 300-mil

D3402

Abstract: 74ACT16245
Contextual Info: 54ACT16245, 74ACT16245 16-BIT BUS TRANSCEIVERS WITH 3-STATE OUTPUTS T I0182— D3402, DECEMBER 1989— REVISED MARCH 1990 54ACT16245 . . . WD PACKAGE 74ACT16245 . . . DL PACKAGE Members of the Texas Instruments Widebus Family TOP VIEW Packaged in Shrink Small Outline 300-mil

D3468

Contextual Info: 54ACT16373, 74ACT16373 16-BIT D-TYPE TRANSPARENT LATCHES WITH 3-STATE OUTPUTS TI0150— D3468, MARCH 1990 • Member of the Texas Instruments Wldebus Family 54ACT16373 . . . WD PACKAGE 74ACT16373 . . . DL PACKAGE TOP VIEW Packaged In Shrink Small Outline 300-mll

Contextual Info: 54ACT11353, 74ACT11353 DUAL 1-0F-4 DATA SELECTORS/MULTIPLEXERS WITH 3-STATE OUTPUTS SCAS045A- D3109, JUNE 1988 - REVISED APRIL 1993 54ACT11353. . . J PACKAGE 74ACT11535. . , D OR N PACKAGE Inverting Versions of 54ACT11253 and 74ACT11253 TOP VIEW Permits Multiplexing From N Lines

Contextual Info: 54ACT11191, 74ACT11191 SYNCHRONOUS 4-BIT UP/DOWN BINARY COUNTERS TI0146— D3455, MARCH 199« 54ACT11191 . . . J PACKAGE 74ACT11191 . . . D W O R N PACKAGE Inputs are TTL-Voltage Compatible Single Down/Up Count Control Line TOP VIEW Look-Ahead Circuitry Enhances Speed ot

74ACT11086

Contextual Info: 54ACT11086, 74ACT11086 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES T 10185— D3390, N O VEM BER 1969 54ACT11086 . . . J PACKAGE 74ACT11086 . . . D OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout TOP VIEW

54ACT11521

Abstract: 74ACT11521 D2957
Contextual Info: 54ACT11521, 74ACT11521 8-BIT IDENTITY COMPARATORS SCAS023A – D2957, JULY 1978 – REVISED APRIL 1993 • • • • • • • Compares Two 8-Bit Words Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations

ACTQ04

Abstract: 54ACTQ04 E20A J14A
Contextual Info: 54ACTQ04 Quiet Series Hex Inverter General Description The ’ACTQ04 contains six inverters and utilizes NSC Quiet Series technology to guarantee quiet output switching and improved dynamic threshold performance. FACT Quiet Series features GTO™ output control and undershoot corrector in addition to a split ground bus for superior ACMOS performance.

54ACTQ16240

Abstract: WA48A
Contextual Info: 54ACTQ16240 16-Bit Inverting Buffer/Line Driver with TRI-STATE Outputs General Description Features The ’ACTQ16240 contains sixteen inverting buffers with TRI-STATE outputs designed to be employed as a memory and address driver, clock driver, or bus-oriented transmitter/

54ACTQ657

Contextual Info: 54ACTQ657 Quiet Series Octal Bidirectional Transceiver with 8-Bit Parity Generator/Checker and TRI-STATE Outputs General Description Features The ACTQ657 contains eight non-inverting buffers with TRI-STATE outputs and an 8-bit parity generator/checker. Intended for bus oriented applications, the device combines

54ACT

Abstract: 54ACT573 ACT373 ACT573
Contextual Info: 54ACT573 Octal Latch with TRI-STATE Outputs General Description Features The ’ACT573 is a high-speed octal latch with buffered common Latch Enable LE and buffered common Output Enable (OE) inputs. n ICC and IOZ reduced by 50% n Inputs and outputs on opposite sides of package

54ACTQ377

Abstract: E20A
Contextual Info: 54ACTQ377 Octal D Flip-Flop with Clock Enable General Description Features The ACTQ377 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common buffered Clock CP input loads all flip-flops simultaneously, when the Clock Enable (CE) is LOW.