4X CMU CLOCK MHZ Search Results

Contextual Info: VSC8146 Datasheet FEATURES ● STS-48/STM-16, FEC ● On-board FIFO ● Wide-ranging PLLs ● Equipment and Facility Loopback modes ● Exceeds Telcordia SONET jitter specifications ● Rx/Tx internal Loop Timing mode ● High-speed data I/O and clock outputs

Contextual Info: VSC8147 Datasheet Features • • • • • • • STS-48/STM-16, FEC Wide-ranging PLLs Exceeds Telcordia SONET jitter specifications High-speed data I/O and clock outputs High-speed clock output power-down option Low-speed 4-bit LVDS I/O LOS and LOL detect with automatic Lock to

10Gbase-kr backplane connector

Abstract: BCM8073 broadcom serdes data eye 1000BaseKX 10Gbase-kr transmitter LSI serdes CMOS CML 10G KR PHy 10GBASE-KR 1000BASE-KX Backplane 10Gbase KR
Contextual Info: BCM8073 Brief DUAL-CHANNEL SERIAL 10GBASE-KR TO XAUI TRANSCEIVER SUMMARY OF BENEFITS FEATURES • Two 10G-XAUI™ interfaces in one compact package • Targeted to meet the IEEE 802.3ap standard • High-performance DFE/FFE receive equalizer with full

bcm8071

Abstract: 1000BASE-KX Backplane 10G serdes 2.5 xaui 1000BaseKX 10G KR PHy 8b/10b encoder gearbox XAUI 1000BASE-X 4X CMU clock mhz
Contextual Info: BCM8071 SERIAL 10G BASE-KR TO XAUI BACKPLANE TRANSCEIVER SUMMARY OF BENEFITS FEATURES • New 10 GbE serial transceiver supporting high-bandwidth • Targeted to meet the draft IEEE 802.3ap standard backplane requirements • High performance DFE/FFE receive equalizer with full

clock generator using ic 555

Abstract: 8B10B ORT82G5 TCLD0110G TETH0110G TMOD0110G TTIA0110G encoder gbit 4X CMU clock mhz
Contextual Info: Product Brief September 2001 TETH0110G 10 Gbit/s Ethernet Serial LAN PHY Features • ■ ■ ■ Overview The TETH0110G is a physical layer device that implements the physical coding sublayer PCS and physical media attachment (PMA) functions for an IEEE 802.3ae 10 Gbit/s Ethernet serial local area

Contextual Info: xr XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER JANUARY 2005 REV. P1.0.3 GENERAL DESCRIPTION AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET

1000kA

Abstract: block diagram of automatic flush system 0X00H
Contextual Info: áç PRELIMINARY XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER DECEMBER 2003 REV. P1.0.2 GENERAL DESCRIPTION an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip

am transmitter circuit diagram and hw to make it

Abstract: STM-16 XRT91L80 XRT91L80IB tms fifo 4bit
Contextual Info: xr XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER MARCH 2005 REV. P1.0.4 GENERAL DESCRIPTION AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET

STM-16

Abstract: XRT91L81 XRT91L81IB STM-16 LIU B30 ferrite
Contextual Info: PRELIMINARY XRT91L81 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER JANUARY 2004 REV. P1.0.3 GENERAL DESCRIPTION an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET and LOSDET output signals. An on-chip

STM-16

Abstract: XRT91L80 XRT91L80IB
Contextual Info: xr XRT91L80 PRELIMINARY 2.488/2.666GBPS OC-48/STM-16 SONET/SDH TRANSCEIVER OCTOBER 2004 REV. P1.0.2 GENERAL DESCRIPTION AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of the LOCKDET

DWDM ITU Frequency Chart

Abstract: SONET "Error correction" STM-16 LIU stm-16 timing source GR-253 STM-16 STS-48 XRT91L80 "Overflow detection" 2666 rev e
Contextual Info: xr XRT91L80 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JANUARY 2007 REV. 1.0.0 GENERAL DESCRIPTION control of the FIFO_AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status of

GR-253

Abstract: STM-16 STS-48 XRT91L80 10P110 K 2666
Contextual Info: xr XRT91L80 PRELIMINARY 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER JULY 2005 REV. P1.1.0 GENERAL DESCRIPTION control of the FIFO_AUTORST pin can automatically recover from an overflow condition. The operation of the device can be monitored by checking the status

EP4SE

Abstract: FBGA 1760 EP4SGX ordering information 3G-SDI serializer CMOS applications handbook DDR SDRAM HY EP4SE230 EP4SE820 L1 F45 EP4SGX70
Contextual Info: 1. Stratix IV Device Family Overview SIV51001-3.1 Altera Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor

Contextual Info: VSC8142 Data Sheet FEATURES ● Integrated clock and data recovery ● Extended multirate support for: • • • • STS-3/STM-1, STS-12/STM-4, STS-48/STM-16, and FEC Gigabit Ethernet 1.25Gb/s and 2.50Gb/s Fibre Channel (1.0625Gb/s and 2.125Gb/s) Fast Ethernet

Contextual Info: TM September 2013 • Overview: 40 minutes − Introduction and Objectives − Overview of Generic Timer Module − Overview of GTM Configuration Tool − Matterhorn/GTM • GTM Configuration Tool Examples Demos: 70 minutes − Building − TOM code with the GTM Configuration Tool

higig pause frame

Abstract: verilog code for 128 bit AES encryption OF IC 741 tsmc design rule 40-nm cyclone V
Contextual Info: 1. Stratix IV Device Family Overview SIV51001-3.1 Altera Stratix® IV FPGAs deliver a breakthrough level of system bandwidth and power efficiency for high-end applications, allowing you to innovate without compromise. Stratix IV FPGAs are based on the Taiwan Semiconductor

Contextual Info: Stratix IV Device Handbook Volume 2: Transceivers 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V2-4.4 2012 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

k241

Abstract: CBB 69 capacitor
Contextual Info: Stratix IV Device Handbook Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V2-3.1 Copyright 2009 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other

HD-SDI over sdh

Abstract: pcie Gen2 payload tx2/rx2 HIV53001-1
Contextual Info: Section I. Transceiver Architecture This section provides a description of transceiver architecture and dynamic reconfiguration for the HardCopy IV device family. This section includes the following chapters: • Chapter 1, HardCopy IV GX Transceiver Architecture

prbs generator

Abstract: STM-16 LIU 4X CMU clock mhz XRT91L82
Contextual Info: JUNE 2007 REV - 1.0.0 Network and Transmission XRT91L82 Datasheet NOTES: II XRT91L82 REV - 1.0.0 2.488/2.666 GBPS STS-48/STM-16 SONET/SDH TRANSCEIVER TABLE OF CONTENTS TABLE OF CONTENTS . III

circuit diagram of rf transmitter and receiver

Abstract: 10G BERT 5.7 GHz RF transciever remote control transmitter and receiver circuit transmitter radio controlled with seven functions video transmitter 2.4 GHz CDR 211 AC EP4S100G4 HD-SDI over sdh pcie Gen2 payload
Contextual Info: Section I. Transceiver Architecture This section provides a description of transceiver architecture and transceiver clocking for the Stratix IV device family. It also describes configuring for multiple protocols and data rates, reset control and power down, and dynamic reconfiguration

HIV53001-1

Abstract: CAN BUS megafunction
Contextual Info: 1. HardCopy IV GX Transceiver Architecture HIV53001-1.0 Introduction This chapter provides details about HardCopy IV transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. HardCopy IV GX devices deliver a very high level of system bandwidth and power

10G BERT

Abstract: altgx bc 201 transistor match line match sense signal EP4S40G5H40 hd-SDI deserializer LVDS HD-SDI over sdh circuit diagram of rf transmitter and receiver GT 6 N 170 k28 60 pcie Gen2 payload
Contextual Info: 1. Stratix IV Transceiver Architecture SIV52001-4.l This chapter provides details about Stratix IV GX and GT transceiver architecture, transceiver channels, available modes, and a description of transmitter and receiver channel datapaths. f For information about upcoming Stratix IV device features, refer to the Upcoming

10G BERT

Abstract: circuit diagram of rf transmitter and receiver HD-SDI over sdh SDH 209 remote control transmitter and receiver circuit 5 channel RF transmitter and Receiver circuit CDR 211 AC circuit diagram of PPM transmitter and receiver circuit diagram video transmitter and receiver core i3 mother board circuit
Contextual Info: Stratix IV Device Handbook Volume 2 101 Innovation Drive San Jose, CA 95134 www.altera.com SIV5V2-4.1 Copyright 2010 Altera Corporation. All rights reserved. Altera, The Programmable Solutions Company, the stylized Altera logo, specific device designations, and all other