4-BIT PARITY/GENERATOR CHECKER DESIGN Search Results

Contextual Info: 54ACT11853, 74ACT11853 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS T I0 1 77— 0 3 4 7 4 , MARCH 1090 54ACT11853 . - JT PACKAGE 74ACT11853 . DW or NT PACKAGE TOP VIEW • Inputs are TTL-Voltage Compatible • High-Speed Bus Transceivers with Parity Generator/Checker

Contextual Info: 54AC11833, 74AC11833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS T 10165— D 3448, MARCH 1990 High-Speed Bus Transceivers with Parity Generator/Checker 5 4A C 11 8 33 . . . J T P ACKA G E 7 4 A C 11833 . . . D W OR N T P ACKA G E TO P V IE W Parity-Error Flag Open-Draln Output

C444G

Abstract: 480T
Contextual Info: fax id: 7012 C Y 5 4 / 7 4 F C T 4 8 0 T Dual 8-Bit Parity Generator/Checker * Two 8-bit parity generator/checkers Featu res * Function, p in o u t and drive co m p a tible with FCT and F logic * FCT-A speed at 7.5 ns max. C o m ’ l FCT-B speed at 5.6 ns max. (C o m ’ l)

Contextual Info: 74ACT280 9 BIT PARITY GENERATOR/CHECKER . HIGH SPEED: tpD =4 ns TYP. at Vcc =5V • LOW POWER DISSIPATION: Icc = 4 |oA (MAX.) at T a = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V(MAX) . 50i2 TRANSMISSION LINE DRIVING CAPABILITY . SYMMETRICAL OUTPUT IMPEDANCE:

dba options me

Contextual Info: SN74ALS29833 8-BIT TO 9-BIT PARITY BUS TRANSCEIVERS D2990, F E B R U A R Y 1987 - R EV ISED O C T O B E R 1991 I • Functionally Similar to AMD Am29833 I I • High-Speed Bus Transceivers with Parity Generator/Checker | S N 7 4 A L S '. . . D W O R N T P A C K A G E

MC10177

Abstract: MC10216 MC10194 MC10170 MC10171 MC10172 MC10173 MC10175 MC10176 MC10178
Contextual Info: Function 9 — 2-Bit Parity Generator-Checker Dual Binary to 1-4 Decoder Low Dual Binary to 1-4 Decoder (High) Quad 2-Input Multiplexer/Latch Dual 4 to 1 Multiplexer Q uint Latch Hex " D " Master-Slave Flip-Flop Triple M E C L to N M O S Translator Binary Counter

74ACT280

Abstract: 74ACT280B 74ACT280M 74ACT280MTR 74ACT280TTR TSSOP14
Contextual Info: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING

TTL 74-series IC

Abstract: 74ACT280 74ACT280B 74ACT280M 74ACT280MTR 74ACT280TTR TSSOP14
Contextual Info: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING

Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker V cc"4 Type Features: • B uffered inputs u Typical propagation delay: 10 ns @ V Cc = 5 V, T, = 25°C, CL = 50 pF GND- 7 FUNCTIONAL DIAGRAM The RCA CD54/74AC280 and CD54/74ACT280 9 -b it o d d /

74ac280

Contextual Info: T e c h n ic a l D a la - . . CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker X CVCN t 01» NC.3 Vç ç 9 2 CS-5M H » 4 ONO» T Type Features: • Buffered inputs m Typical propagation delay: 10 ns @ Vcc = 5 V, U = 25° C, C l = 50 pF FUNCTIONAL DIAGRAM

SN64BCT657

Contextual Info: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCBS090A – NOVEMBER 1991 – REVISED JANUARY 1994 • • • • • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V

4 bit even parity generator circuit

Abstract: 4 bit even and odd parity checker truth table PLS153 SU-210 PLS153A AN021 application of parity checker
Contextual Info: Philips Semiconductors Programmable Logic Devices Application Note 9-Bit parity generator/checker with PLS153/153A AN021 INTRODUCTION This application note presents the design of a parity generator using Philips Semiconductors PLD, PLS153 or PLS153A, which enables the designers to customize

SN64BCT657

Abstract: SN64BCT657DW SN64BCT657NT
Contextual Info: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCBS090A – NOVEMBER 1991 – REVISED JANUARY 1994 • • • • • State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015; Exceeds 200 V

SN64BCT657

Contextual Info: SN64BCT657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3ĆSTATE OUTPUTS SCBS090A − NOVEMBER 1991 − REVISED JANUARY 1994 • • • • • DW OR NT PACKAGE TOP VIEW State-of-the-Art BiCMOS Design Significantly Reduces ICCZ ESD Protection Exceeds 2000 V Per

X3.28 nak

Contextual Info: Signetics SCN2653/SCN68653 Polynomial Generator Checker PGC Product Specification Microprocessor Products DESCRIPTION FEATURES The Signetics SCN2653/68653 Polyno­ mial Generator Checker (PGC) Is a poly­ nomial generator ch e c k e r/c h a ra c te r comparator circuit that complements a

74ACT11657

Abstract: A1273
Contextual Info: 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCAS232 – AUGUST 1992 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin

74ACT11657

Abstract: A1273
Contextual Info: 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCAS232 – AUGUST 1992 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin

ABT657A

Contextual Info: SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS _ S C BS192C-JANUARY 1991 - REVISED JANUARY 1997 State-of-the-Art EPIC-UB BiCMOS Design Significantly Reduces Power Dissipation

DM93S62N

Abstract: MS-001 N14A DM93S62
Contextual Info: DM93S62 9-Input Parity Checker/Generator October 1988 Revised May 2000 DM93S62 9-Input Parity Checker/Generator General Description The DM93S62 is a very high speed 9-input parity checker/ generator for use in error detection and error correction applications. The DM93S62 provides odd and even parity

vhdl code for 8-bit parity checker

Abstract: vhdl code for 8 bit odd parity checker vhdl code for parity checker CRC-16 and CRC-32 vhdl code CRC vhdl code for 8-bit odd parity checker 04C11DB7 vhdl code CRC 32 h8005 CRC Generator/Checker
Contextual Info: crc MegaCore Function Parameterized CRC Generator/Checker April 1999, ver. 2 Features Data Sheet • ■ ■ ■ ■ ■ General Description crc MegaCoreTM function, general-purpose cyclic redundancy code CRC generator and checker Optimized for the FLEX® device architecture

DM93S62

Abstract: DM93S62N N14A
Contextual Info: DM93S62 9-Input Parity Checker/Generator General Description The DM93S62 is a very high speed 9-input parity checker/ generator for use in error detection and error correction applications. The DM93S62 provides odd and even parity for up to nine data bits. The even parity output PE is HIGH if an

MD15and

Abstract: SU16
Contextual Info: FUJITSU M I C R O E L E C T R O N I C S °il F U J IT S U D e | 3 7 ^ 7 1 ^ QOD4t.7S 3 | 16 BIT ERROR «CHECKING & CORRECTION T-^ S-i7 -MB1426 I _ 1 A p ril, 1986 E d itio n 1.0 DESCRIPTION The MB1426 Error Checking and Correction ECC device is designed to

abt657a

Contextual Info: SN54ABT657A, SN74ABT657A OCTAL TRANSCEIVERS WITH PARITY GENERATORS/CHECKERS AND 3-STATE OUTPUTS SCBS192E – JANUARY 1991 – REVISED JUNE 1997 D D D D D D D State-of-the-Art EPIC-ΙΙB  BiCMOS Design Significantly Reduces Power Dissipation ESD Protection Exceeds 2000 V Per

74ACT11657

Contextual Info: 74ACT11657 OCTAL TRANSCEIVER WITH PARITY GENERATOR/CHECKER AND 3-STATE OUTPUTS SCAS232 – AUGUST 1992 – REVISED APRIL 1993 • • • • • • Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Pin