4 INPUTS POSITIVE OR GATES Search Results
4 INPUTS POSITIVE OR GATES Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| 5433J/B |
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5433 - Quad 2-Input Pos-NOR Buffers (OC) |
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| 54S133/BEA |
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54S133 - NAND GATE, 13-INPUT - Dual marked (M38510/07009BEA) |
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| 54ACTQ32/QCA |
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54ACTQ32 - OR Gate, ACT Series, 4-Func, 2-Input, CMOS, - Dual marked (5962-8973601CA) |
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| 5409/BCA |
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5409 - AND GATE, QUAD 2-INPUT, WITH OPEN-COLLECTOR OUTPUTS - Dual marked (M38510/01602BCA) |
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| 54HC30/BCA |
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54HC30 - 8-Input NAND Gates - Dual marked (M38510/65004BCA) |
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4 INPUTS POSITIVE OR GATES Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B QUAD 2 INPUT OR GATE TC4072B DUAL 4 INPUT OR GATE TC4075B TRIPLE 3 INPUT OR GATE TC4071B, TC4075BP / BF and TC4072BP / BF are positive logic OR gates w ith tw o inputs, three inputs and fo ur inputs |
OCR Scan |
TC4071BP/BF/BFNJC4072BP/BF TC4075BP/BF TC4071B TC4072B TC4075B TC4071B, TC4075BP TC4072BP TC4071B | |
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Contextual Info: GD54/74LS20 DUAL 4-INPUT POSITIVE NAND GATES Description This device contains two independent 4-input NAND gates. It performs the Boolean functions y = A B-C D or Y = A + B + C + D in positive logic. Function Table each gate INPUTS OUTPUT N* V L L H H L |
OCR Scan |
GD54/74LS20 | |
D2967
Abstract: 74ACT11032 D2957 364Bh 54ACT11032
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OCR Scan |
54ACT11032, 74ACT11032 TP0061â D2957, 500-mA 300-mil 54ACT11032 D2967 74ACT11032 D2957 364Bh | |
CT1102
Abstract: 54ACT11020 74ACT11020 D2957 692B
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OCR Scan |
54ACT11020, 74ACT11020 SCAS016A D2957, 500-mA 300-mll 54ACT11020. 74ACT11020 T4EC11 CT1102 54ACT11020 D2957 692B | |
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Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
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SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 | |
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Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
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SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 | |
A115-A
Abstract: C101 SN54AHC132 SN74AHC132 HA132
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SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 A115-A C101 SN54AHC132 SN74AHC132 HA132 | |
A115-A
Abstract: C101 SN54AHC132 SN74AHC132
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SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 A115-A C101 SN54AHC132 SN74AHC132 | |
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Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
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SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 | |
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Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
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SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 | |
HA132
Abstract: A115-A C101 SN54AHC132 SN74AHC132
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SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 HA132 A115-A C101 SN54AHC132 SN74AHC132 | |
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Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
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SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 | |
SCLS365
Abstract: A115-A C101 SN54AHC132 SN74AHC132
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SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 SCLS365 A115-A C101 SN54AHC132 SN74AHC132 | |
ha132
Abstract: A115-A C101 SN54AHC132 SN74AHC132
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SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 ha132 A115-A C101 SN54AHC132 SN74AHC132 | |
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Contextual Info: 54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES TI0053— D 2957, JUNE 1987— REVISED JANUARY 1990 • Inputs are TTL-Voltage Compatible 54ACT11020 . . . J PACKAGE 74ACT11020 . . . D OR N PACKAGE • Flow-Through Architecture to Optimize PCB Layout |
OCR Scan |
54ACT11020, 74ACT11020 TI0053-- 54ACT11020 74ACT11020 500-mA 300-mil | |
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Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
Original |
SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 | |
A115-A
Abstract: C101 SN54AHC132 SN74AHC132 HA132
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Original |
SN54AHC132, SN74AHC132 SCLS365G SN54AHC132 A115-A C101 SN54AHC132 SN74AHC132 HA132 | |
HA132Contextual Info: SN54AHC132, SN74AHC132 QUADRUPLE POSITIVE-NAND GATES WITH SCHMITT-TRIGGER INPUTS SCLS365G – MAY 1997 – REVISED SEPTEMBER 2002 SN54AHC132 . . . J OR W PACKAGE SN74AHC132 . . . D, DB, DGV, N, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC |
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SN54AHC132, SN74AHC132 SCLS365G AHC00 000-V A114-A) A115-A) SN54AHC132 AHC132 HA132 | |
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Contextual Info: 54ACT11032, 74ACT11032 QUADRUPLE 2-INPUT POSITIVE-OR GATES T10061— D2957, JULY 1987—REVISED MARCH 1990 • Inputs are TTL-Voltage Compatible 5 4 A C T 11 0 32 . . . J P ACKA G E 7 4 A C T 11 0 32 . . . O OR N P ACKA G E • Flow-Through Architecture to Optimize PCB |
OCR Scan |
54ACT11032, 74ACT11032 T10061-- D2957, 1987--REVISED 500-mA 300-mil | |
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Contextual Info: 54ACT11021, 74ACT11021 DUAL 4-INPUT POSITIVE-AND GATES SCAS012B - P2957, JULY 1978 - REVISED APRIL 1993 54ACT11021 . . . J PACKAGE 74ACT11021 . . . D OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-PIn V^c and GND Configurations |
OCR Scan |
54ACT11021, 74ACT11021 SCAS012B P2957, 500-mA 300-mil 54ACT11021 to125 | |
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Contextual Info: 54ACT11020,74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES SCAS016A - 02957, JUNE 1987 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible 54ACT11020. . . J PACKAGE 74ACT11020. . . D OR N PACKAGE TOP VIEW Flow-Through Architecture to Optimize PCB Layout Center-Pin Vqc and GND Configurations to |
OCR Scan |
54ACT11020 74ACT11020 SCAS016A 500-mA 300-mil 54ACT11020. 74ACT11020. 54ACT11020 | |
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Contextual Info: CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES SCHS320 – NOVEMBER 2002 D D D D D D CD54ACT20 . . . F PACKAGE CD74ACT20 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption |
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CD54ACT20, CD74ACT20 SCHS320 24-mA MIL-STD-883, CD54ACT20 CD74ACT20 ACT20 | |
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Contextual Info: CD54ACT20, CD74ACT20 DUAL 4-INPUT POSITIVE-NAND GATES SCHS320 – NOVEMBER 2002 D D D D D D CD54ACT20 . . . F PACKAGE CD74ACT20 . . . E OR M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption |
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CD54ACT20, CD74ACT20 SCHS320 24-mA MIL-STD-883, CD54ACT20 CD74ACT20 ACT20 16-Jul-2007 | |
CD74ACT20
Abstract: CD54ACT20 CD54ACT20F3A CD74ACT20E CD74ACT20M CD74ACT20M96 ACT20M
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CD54ACT20, CD74ACT20 SCHS320 CD54ACT20 24-mA MIL-STD-883, ACT20 CD74ACT20 CD54ACT20 CD54ACT20F3A CD74ACT20E CD74ACT20M CD74ACT20M96 ACT20M | |