4 INPUT D FLIP FLOP Search Results

ic 74 hc 10

Contextual Info: GD54/74HC74, GD54/74HCT74 DUAL D-TYPE FLIP-FLOPS WITH PRESET & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 7 4 . They consist of two D-type flip-flops with individual preset, clear, and clock inputs. Infor­ mation at a D-input is transferred to the correspon­

74HC273

Abstract: 54HC273
Contextual Info: SN54HC273, SN74HC273 OCTAL D TYPE FLIP-FLOPS WITH CLEAR D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1 9 8 7 Contains Eight Flip-Flops with Single-Rail Outputs T O P V IE W • Individual Data Input to Each Flip-Flop • Applications Include: Buffer/Storage Registers

74HC273

Abstract: 54HC273 VJ20 SM74HC273
Contextual Info: SN54HC273, SN74HC273 OCTAL D TYPE FLIP-FLOPS WITH CLEAR D 2 6 8 4 , DECEMBER 1 9 8 2 - REVISED JUNE 19B9 Contains Eight Flip-Fiops with Single-Rail Outputs SN 54H C273 . . . J PACKAGE SN74HC273 . DW OR N PACKAGE ITOP VIEW CLR n • Individual Data Input to Each Flip-Flop

M74LS175P

Abstract: 12 V T flip flop IC 20-PIN
Contextual Info: MITSUBISHI LSTTLs M74LS175P QUADRUPLE D -TY P E FLIP FLOP W IT H RESET DESCRIPTION The M 74L S 17 5P PIN CONFIGURATION TOP VIEW is a semiconductor integrated circuit containing 4 positive edge-triggered D -type flip-flops w ith common clock input T and direct reset input R q and

Contextual Info: HITACHI/ LOGIC/ARRAYS/ IEM 4 ^ 5 0 3 IE 92D - HD7 4 HC174 # DOlDWai 3 10421 T-46-07-1Û D Hex D-type Flip-Flops (with Clear) This device contains 6 master-slave flip-flops with a common • PIN ARRANGEMENT clock and common dear. Data on the D input having the

Contextual Info: C2MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC T C 4 TC407 6 B P 7 6 B P 4 -BIT D-TYPE REGISTER TC4076BP is the register which consists of four D type flip-flops having 3-stage outputs, and these four flip-flops are controlled by common CLOCK input and

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM HE HD74HC273 # DËJ 44Tb2Q3 QQIQHTt. Octal D-type Flip-Flops with Clear 92D This device contains 8 master-slave flip-flops with a common d o c k and common clear. Data on the D input having the | 10476 D T -4 6 -0 7 -1 1 PIN ARRANGEMENT

Contextual Info: GD54/74HC175, GD54/74HCT175 QUAD D-TYPE FLIP-FLIPS WITH COMMON CLOCK & CLEAR General Description These devices are identical in pinout to the 5 4 /7 4 L S 1 7 5 . They contain four D-type flip-flops with common clock and clear inputs, and separate data inputs. Information at a data input is

14521B

Abstract: HD14521
Contextual Info: H D 14521B 2 4 - S tage Frequency Divider The HD 1452IB consists o f a chain o f 24 flip-flops with an input circuit that allows three m odes o f operation. The input will function as a crystal oscillator, an RC oscillator, or as an input buffer for an external oscillator. Each flip-flop divides the frequency o f the

Contextual Info: S ANYO SEMICONDUCTOR CORP 12 E D I 0002751 3 T - 4 ^ 0 7 - 1 C M O S High-Speed Standard Logic LC74HC Senes 3021B Octal 3-State Noninverting D-Type Flip-Flop £*2078 Features The LC74HC374 consists of 8 identical noninverting D-type flip-flops with 3-statfcoutputs. The clock input CLK)

HD74LS173

Contextual Info: HD74LS173• 4-Bit D-Type Registers with three-state outputs respective flip-flops on the next positive transition of the buf­ fered clock input. Gate output control inputs are also pro­ The HD74LS173 four-bit register includes D-type flip-flops featuring totempole three-state outputs capable of driving

74AUP1G79GW

Abstract: 74AUP1G79 74AUP1G79GF 74AUP1G79GM
Contextual Info: 74AUP1G79 Low-power D-type flip-flop; positive-edge trigger Rev. 4 — 20 July 2010 Product data sheet 1. General description The 74AUP1G79 provides the single positive-edge triggered D-type flip-flop. Information on the data input is transferred to the Q output on the LOW-to-HIGH transition of the clock

TC4076BP

Abstract: TC4076
Contextual Info: TC4076BP C 2M O S DIGITAL IN T E G R A T E D CIRCUIT SIL IC O N M O N O LITH IC TC4076BP 4-BIT D-TYPE REGISTER TC4076BP is the register which consists of four D type flip-flops having 3-stage outputs, and these four flip-flops are controlled by common CLOCK input and

LA 4303

Abstract: MM74HC4303 54HC MM54HC4303 74HC4303 LA+4303
Contextual Info: M M 5 4 H C 4 3 0 3 / M M 7 4 H C 4 3 0 3 TTL Input O ctal TRI-STATE Flip-Flop W ith Inverting Outputs General Description This high sp ee d OCTAL D-TVPE FLIP-FLO P is m a nu fac­ tu re d w ith s ilic o n gate C M OS te ch n o lo g y. All inp u ts are co m p a tib le w ith TTL lo g ic le ve ls, re co g n izin g a ze ro input

iC4013BP

Abstract: ic4013 TG40 TG-40 R S flip flop TG401
Contextual Info: TC4013BP/BF C 2M O S D IG IT A L I N T E G R A T E D C IR C U IT SIL IC O N M O N O LIT H IC IC4013BP/TC4013BF DUAL D-TYPE FLIP FLOP T C 4 0 1 3 B P / B F contains two independent circuits of D type flip-flop. The input level applied to DATA input are transferred to Q and Q" output by r i s ­

Contextual Info: HITACHI/ LO GI C/ AR R A Y S/ M E N T5 HD 74 HC 114 D E I 4 4 ^ 2 0 3 001D373 7 | “ 92D 10373 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock T - % '0 - i - 0 7 This flip -fio p is edge sensitive to the clock input and change PIN ARRANGMENT

NO18U

Abstract: LC4913 361-s j10V
Contextual Info: S AN Y O SEMICONDUCTOR CORP ia E D I 7 cj Iì 7 D 7[3 O D O a f l i l ‘._!T-St-0'7-08 3003A Original C M O S Standard Logic L C 4 9 0 0 B Series Dual D-Type Flip-Flop with Schmitt Clock Input 1843A The LC4913 is a dual D-type flip-flop having such features as wide operating

rtl micrologic 900

Abstract: fairchild 946 HALF ADDER fairchild rtl DTL Fairchild 946 DTL Fairchild 930 Fairchild 958 counter rtl decade counter RTL DTL logic 937 fairchild
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

HALF ADDER

Abstract: rtl micrologic 900 fairchild rtl Fairchild DTL 936 rtl nand gate 926 rtl micrologic fairchild micrologic 960 rtl inverter 4 bit binary half adder
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

fairchild 946

Abstract: 930 dtl fairchild rtl DTL Fairchild 930 rtl micrologic 900 dtl 930 Fairchild 936 DTL Fairchild rtl micrologic fairchild 932
Contextual Info: FAIRCHILD DIGITAL RTL/CTL DEVICE NO. Logic/Connection Diagram Package s Buffer F8 3F.5B 14 913 D Flip-Flop F6 3F.5B Counter Adapter F18 3F.5B 15 914 Dual 2-NOR F13 3F.5B 3 902 Flip-Flop F19 3F,5B 16 915 Dual 3-NOR F14 3F.5F 4 903 3-Input NOR F9 3F,5B 17 921

Contextual Info: Standard ICs Dual 4-bit static shift register B U 4 0 1 5 B /B U 4 0 1 5 B F The BU4015B and BU4015BF are 4-stage static shift registers, each consisting of two circuits. The D flip-flops for each stage share a common reset input, enabling external asynchronous reset at any point.

Contextual Info: SN54HC109, SN74HC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS470 – MARCH 2003 D D D Wide Operating Voltage Range of 2 V to 6 V Low Input Current of 1 µA Max High-Current Outputs Drive Up To 10 LSTTL Loads 1 16 2 15 3 14 4 13

SN54HC109

Abstract: SN74HC109 SN74HC109D SN74HC109DR SN74HC109N SN74HC109NSR SNJ54HC109FK SNJ54HC109J SNJ54HC109W
Contextual Info: SN54HC109, SN74HC109 DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOPS WITH CLEAR AND PRESET SCLS470 – MARCH 2003 D D D Wide Operating Voltage Range of 2 V to 6 V Low Input Current of 1 µA Max High-Current Outputs Drive Up To 10 LSTTL Loads 1 16 2 15 3 14 4 13

Contextual Info: 7 4 H C /H C T 5 3 4 MSI OCTAL D-TYPE FLIP-FLOP; POSITIVE EDGE-TRIGGER; 3-STATE; INVERTING FEA TU R ES • • • • • TYPICAL 3*state inverting outputs for bus oriented applications 8-bit positive, edge-triggered register Common 3-state output enable input