4 CHANNEL SLIC Search Results

Contextual Info: XRT73LC04A 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2003 REV. 1.0.0 GENERAL DESCRIPTION The XRT73LC04A, 4-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L04A and consists of four independent line transmitters and receivers integrated on a single chip

Contextual Info: áç XRT73L04 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2001 REV. 1.2.0 GENERAL DESCRIPTION The XRT73L04, 4-Channel, DS3/E3/STS-1 Line Interface Unit consists of four independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications.

0x02-0x03

Abstract: 73L04
Contextual Info: áç XRT73L04 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT APRIL 2001 REV. 1.1.0 GENERAL DESCRIPTION The XRT73L04, 4-Channel, DS3/E3/STS-1 Line Interface Unit consists of four independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications.

Contextual Info: XRT73L04B 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT JULY 2003 REV. 1.0.0 GENERAL DESCRIPTION The XRT73L04B, 4-Channel, DS3/E3/STS-1 Line Interface Unit is a low power CMOS version of the XRT73L04A and consists of four independent line transmitters and receivers integrated on a single chip

SAA7164

Abstract: SAA7163 BGA364 LBGA256 video processor comb filter nxp tv tuner
Contextual Info: NXP Single-/Dual-channel Audio/ Video Decoder and Compression Engine, SAA7163/4 Integrated solution for DVR and time shifting in Consumer Electronics applications The single-/dual-channel audio/video decoder IC, SAA7163/4 enables TV and STB manufacturers to add a hard disk drive for Digital Video Recording DVR and time shift.

Contextual Info: áç XRT73L04 PRELIMINARY 4 CHANNEL DS3/E3/STS-1 LINE INTERFACE UNIT SEPTEMBER 2000 REV. P1.0.5 GENERAL DESCRIPTION The XRT73L04, 4-Channel, DS3/E3/STS-1 Line Interface Unit consists of four independent line transmitters and receivers integrated on a single chip designed for DS3, E3 or SONET STS-1 applications.

CD4514BC

Abstract: CD4514BCN CD4514BCWM CD4515BC CD4515BCN CD4515BCWM M24B MC14514 MC14515 N24A
Contextual Info: Revised January 1999 CD4514BC• CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS CMOS circuits constructed with N- and P-channel

32P4103H

Abstract: hard disk head preamp viterbi
Contextual Info: SSI 32P4103H PRML Read Channel with EPR4, 16/17 0,6/8 ENDEC, 4-Burst Servo September 1998 • Register programmable dynamic power management (<5 mW power down mode) The SSI 32P4103H is a high performance BiCMOS read channel IC that provides all of the functions

32P4104B

Abstract: hard disk head preamp viterbi
Contextual Info: SSI 32P4104B PRML Read Channel with EPR4, 16/17 0,6/8 ENDEC, 4-Burst Servo April 1999 • Register programmable dynamic power management (<10 mW power down mode) The SSI 32P4104B is a high performance BiCMOS read channel IC that provides all of the functions

32P4104H

Abstract: hard disk head preamp viterbi
Contextual Info: SSI 32P4104H PRML Read Channel with EPR4, 16/17 0,6/8 ENDEC, 4-Burst Servo February 1999 • Register programmable dynamic power management (<10 mW power down mode) The SSI 32P4104H is a high performance BiCMOS read channel IC that provides all of the functions

mc14514

Abstract: cd4514
Contextual Info: Revised January 2004 CD4514BC • CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS CMOS circuits constructed with N- and P-channel

circuits of cd4514

Abstract: Applications of decoder CD4514 CD4514 CD4514BCN MC14515 mc14514 CD4514BC CD4514BCWM CD4515BC CD4512
Contextual Info: Revised January 2004 CD4514BC • CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features The CD4514BC and CD4515BC are 4-to-16 line decoders with latched inputs implemented with complementary MOS CMOS circuits constructed with N- and P-channel

32P4103S

Abstract: hard disk head preamp viterbi Fly DS 100
Contextual Info: SSI 32P4103S PRML Read Channel with EPR4, 16/17 0,6/8 ENDEC, 4-Burst Servo February 1999 • Register programmable dynamic power management (<10 mW power down mode) The SSI 32P4103S is a high performance BiCMOS read channel IC that provides all of the functions

GN2406

Abstract: GN1153 epon 828 GN2405 GN2004S GN2003S GN1153B GN1113 GN3250 GN1250L
Contextual Info: Optical and IC Products for High Speed Communications 2009 Product Guide High Performance contents Intro 1 What’s New 3 Optical & Copper Form Factors 4 Products TIAs 5 ROSAs 6 Single-Channel CDRs 7 Multi-Channel Signal Conditioners 8 Laser Drivers and Limiting Amplifiers

Contextual Info: www.ti.com TVP5154 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK SLES163A – MARCH 2006 – REVISED JULY 2006 1 Introduction 1.1 Features • • • • • • • Four Separate Video Decoder Channels With Features for Each Channel:

mc14514

Abstract: CD4514B CD4514BM CD4515B CD4515BM MC14515 5 to 32 decoder using 4 t0 16 decoders CD4512
Contextual Info: February 1988 CD4514BM/CD4514BC, CD4515BM/CD4515BC 4-Bit Latched/4-to-16 Line Decoders General Description Features The CD4514B and CD4515B are 4-to-16 line decoders with latched inputs implemented with complementary MOS CMOS circuits constructed with N- and P-channel en­

128-PIN

Abstract: TVP5145 TVP5146 TVP5147 TVP5150 TVP5150AM1 TVP5154 TVP5154PNP TVP5160
Contextual Info: www.ti.com TVP5154 4-CHANNEL LOW-POWER PAL/NTSC/SECAM VIDEO DECODER WITH INDEPENDENT SCALERS AND FAST LOCK SLES163A – MARCH 2006 – REVISED JULY 2006 1 Introduction 1.1 Features • • • • • • • Four Separate Video Decoder Channels With Features for Each Channel:

TXM TX 2E

Abstract: rdn 100 n 20 550 FX949 JCSR XP35 bl 8176
Contextual Info: c r a i -J CML Semiconductor Products CDPD W ireless Modem Data Pump FX949 D/949/4 August 1995 1.0 Features Advance information • MES Full Duplex Operation • 19.2kb/s GMSK Modulation • Forward Channel Decoding • Sleep Timer Included • Reverse Channel Encoding

CD4514BCN

Abstract: circuits of cd4514 C1995 CD4514B CD4514BC CD4514BM CD4515B CD4515BC CD4515BM MC14514
Contextual Info: CD4514BM CD4514BC CD4515BM CD4515BC 4-Bit Latched 4-to-16 Line Decoders General Description Features The CD4514B and CD4515B are 4-to-16 line decoders with latched inputs implemented with complementary MOS CMOS circuits constructed with N- and P-channel enhancement mode transistors These circuits are primarily

CHN G4 136

Abstract: chn 711 CHN G4 141 CHN G4 124 CHN G4 137 CHN 423
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JANUARY 2007 REV. 1.2.2 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

CHN G4 136

Abstract: CHN G4 117 CHN G4 112 CHN G4 140 wireless 4-bit data transmission using 8051 64126 CHN 523 CHN G4 115
Contextual Info: XRT86VL3x T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION JULY 2006 REV. 1.2.1 GENERAL DESCRIPTION The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology Relayless, Reconfigurable, Redundancy that comes in a 2-channel, 4-channel,

32P4101A

Abstract: hard disk read channel hard disk head preamp viterbi
Contextual Info: SSI 32P4101A PRML Read Channel with EPR4, 16/17 0,6/8 ENDEC, 4-Burst Servo EN TS April 1999 DESCRIPTION • Register programmable dynamic power management (<10 mW power down mode) The SSI 32P4101A is a high performance BiCMOS read channel IC that provides all of the functions

CMX910

Abstract: rx2 G receiver ic remote control AIS marine receiver fsk modulator using 555 fsk modulation using 555 SOTDMA CMX910L9 gps transponder FX604 mobile antenna design
Contextual Info: CMX910 AIS Baseband Processor D/910/4 October 2007 Provisional Issue Features: • Half-Duplex GM F SK, FSK and DSC Capabilities • I and Q Radio Interface • Slot/Sample Counter with UTC Timing Interface • Low-Power (3.0 to 3.6V) Operation • Optimum Co-channel and Adjacent-channel

prml

Abstract: 32P4129 hard disk head preamp viterbi
Contextual Info: SSI 32P4129 PRML Read Channel with EPR4, 16/17 0,6/8 ENDEC, 4-Burst Servo EN TS March 1999 DESCRIPTION • Register programmable dynamic power management (< 5 mW power down mode) The SSI 32P4129 is a high performance BiCMOS read channel IC that provides all of the functions needed to