390TT Search Results

Contextual Info: 9617 TRIPLE EIA RS-232-C LINE RECEIVER FAIRCHILD LINEAR INTEGRATED CIRCU ITS G E N E R A L D E S C R I P T I O N — T he 9 6 1 7 is a m on olithic Triple Line Receiver constructed using the Fairchild Planar* process. It is designed to meet the term inator electrical requirem ents of E I A R S -2 3 2 -C

Contextual Info: Lattice GAL18V10 High Performance E2CMOS PLD Generic Array Logic F U N C T IO N A L B L O C K D IA G R A M FEA TU RES >HIGH PERFORMANCE E2CMOS* TECHNOLOGY — 15 ns Maximum Propagation Delay — Fmax = 62.5 MHz — 10ns Maximum from Clock Input to Data Output