35-158-2 PIN DIAGRAM Search Results

74LS158PC

Abstract: 74S158PC Z1212 54LS158DM 54S158DM 74LS158DC 74LS158FC 74S158DC 74S158FC 74LS158D
Contextual Info: 1 NATIONAL SEdlCOND {LOGIC} DEE D | bS01122 DQb3fi47 ö | _ T-66-21-53 158 CONNECTION DIAGRAM PINOUT A 54S/74S158 54LS/74LS158 •E nr haE QUAD 2-INPUT MULTIPLEXER TÏ1 v c c ioa Ts] ë 2a [ I Í3 ]l,c lo b [s 2]ZC H ]lo c lod lib [ I

REF028

Abstract: CLKB25 AD591 RSVD16 PC PSU CIRCUIT diagram ad54 ad5462 AD42/172Z-0 AD29 AD30
Contextual Info: B Layout and Circuit Diagrams This appendix contains layout and circuit details of the PCI backplane. 1 July 1997 – Subject To Change Layout and Circuit Diagrams B–1 zz001 Figure B–1 Backplane Arrangement in a PC/AT Chassis. B–2 Layout and Circuit Diagrams

2128-80LQ

Contextual Info: ® ispLSI and pLSI 2128 High Density Programmable Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay Output Routing Pool ORP — — — — — — — TTL Compatible Inputs and Outputs

AA13

Abstract: AA19 AC11 AC13 AD12
Contextual Info: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool

AA13

Abstract: AA19 AC11 AC13 AD12
Contextual Info: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool

2128-80LQ

Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5

B272

Abstract: 203d6
Contextual Info: ispLSI 3160 High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

B272

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

203d6

Abstract: B272
Contextual Info: ispLSI 3160 Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

B272

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

Contextual Info: LeadFree a P ckage Options Available! ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay • IN-SYSTEM PROGRAMMABLE D0 C7 A1 ES

Contextual Info: TQ9132-BN Data Sheet Wide Band Power Amplifier Gain Block Features Functional Block Diagram IN 3 6 OUT • • • • • • GND 4 5 GND Applications VDD 1 8 GND GND 2 7 GND TQ9132B Product Description The TQ9132 amplifier is a 500-2500 MHz amplifier capable of providing

Contextual Info: 606HM Transmit Converter Features • Accom m odates either single-rail or dual-rail u n ipolar input ■ Provides the required overshoot on the trailing edge of the DS1 ou tp u t pulse ■ Contains 5 selectable equalizers ■ Provides the line loopback function

606H

Abstract: line code unipolar 5067 16 pin 412SR
Contextual Info: ♦ Data Sheet 606HM Transmit Converter Features • Accommodates either single-rail or dual-rail unipolar input ■ Provides the required overshoot on the trailing edge of the DS1 output pulse ■ Contains 5 selectable equalizers ■ Provides the line loopback function

3.579545

Abstract: HCF0221
Contextual Info: Hvbrid ICs T D K CORP SflE ]> • flfl2124fl □ □OL.Mbb 0T3 ■ TDKA COMB FILTER MODULES FOR Y/C SEPARATION IN NTSC TV AND VCR, HCF SERIES Block diagram GND A = 2.5 ±0.3 [.098±.012] Pin No. 1: Pin No. 2: Pin No. 3: Pin No. 4: Pin No. 5: Dimensions in mm [inches]

AD5375

Abstract: ADL5375ACPZ-05-WP1 MO-220-VGGD-8 ADL5375 multi-band radio frequency ADL5375-05 ADL5375-15 lfcsp_VQ package
Contextual Info: Preliminary Technical Data 400 MHz to 6 GHz Broadband Quadrature Modulator ADL5375 FEATURES FUNCTIONAL BLOCK DIAGRAM Output frequency range: 400 MHz to 6 GHz Modulation bandwidth: 500 MHz 3 dB 1 dB output compression: ≥ 9.4 dBm from 500 MHz to 4 GHz Output return loss: ≤ 15 dB from 500 MHz to 5 GHz

3256E

Contextual Info: ispLSI 3256E High Density Programmable Logic Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

036 84, 036 85, 036 86 rondorex w21

Abstract: kc 59 246 3256E
Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

B272

Abstract: 149-IO
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

B272

Abstract: z 0607
Contextual Info: ispLSI 3192 Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic

3192-70LQI

Abstract: B272
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

B272

Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

Contextual Info: ispLSI 3160 High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

Contextual Info: Specifications ispLSI 3192 ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State