35-158-2 PIN DIAGRAM Search Results

7824 MA datasheet

Contextual Info: TGF2023-2-05 25 Watt Discrete Power GaN on SiC HEMT Applications • Defense & Aerospace • Broadband Wireless Product Features • • • • • • • Functional Block Diagram Frequency Range: DC - 18 GHz 43 dBm Nominal PSAT at 3 GHz 78.3% Maximum PAE

74LS158PC

Abstract: 74S158PC Z1212 54LS158DM 54S158DM 74LS158DC 74LS158FC 74S158DC 74S158FC 74LS158D
Contextual Info: 1 NATIONAL SEdlCOND {LOGIC} DEE D | bS01122 DQb3fi47 ö | _ T-66-21-53 158 CONNECTION DIAGRAM PINOUT A 54S/74S158 54LS/74LS158 •E nr haE QUAD 2-INPUT MULTIPLEXER TÏ1 v c c ioa Ts] ë 2a [ I Í3 ]l,c lo b [s 2]ZC H ]lo c lod lib [ I

Contextual Info: 158 CO NNECTIO N DIAGRAM PINOUT A IS/74S158 6 / o !'J 54LS/74LS158 , / , v .J QUAD 2-INPUT MULTIPLEXER DESCRIPTION — T h e ’158 is a high speed quad 2-input m ultiplexer. It selects fo u r bits of data from tw o sources using the com m on Select and Enable

37 PIN TFT MOBILE DISPLAY

Abstract: Single Chip Microcomputers Ultra mini CMOS camera transistor ck 112 mn1880 39 PIN TFT MOBILE DISPLAY MN194 MN1940
Contextual Info: Contents Type Number List 3 Application Block Diagrams . 21 Video Applications. 23 V C R System. ©TV-VCR Com bination.

54ACT

Abstract: 74AC
Contextual Info: AC158 • ACT 158 54 AC/74 AC 158 • 54ACT/74ACT158 Quad 2-Input Multiplexer Description Connection Diagrams The ’AC/’ACT158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the

REF028

Abstract: CLKB25 AD591 RSVD16 PC PSU CIRCUIT diagram ad54 ad5462 AD42/172Z-0 AD29 AD30
Contextual Info: B Layout and Circuit Diagrams This appendix contains layout and circuit details of the PCI backplane. 1 July 1997 – Subject To Change Layout and Circuit Diagrams B–1 zz001 Figure B–1 Backplane Arrangement in a PC/AT Chassis. B–2 Layout and Circuit Diagrams

Contextual Info: 1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Five Outputs AD9512-EP Enhanced Product FEATURES FUNCTIONAL BLOCK DIAGRAM VS FUNCTION DSYNC DSYNCB SYNCB, RESETB PDB DETECT SYNC GND RSET VREF AD9512-EP PROGRAMMABLE DIVIDERS AND PHASE ADJUST SYNC STATUS

2128-80LQ

Contextual Info: ® ispLSI and pLSI 2128 High Density Programmable Logic Functional Block Diagram • HIGH PERFORMANCE E2CMOS® TECHNOLOGY fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay Output Routing Pool ORP — — — — — — — TTL Compatible Inputs and Outputs

Contextual Info: AC158 • ACT158 54AC/74AC158 • 54ACT/74ACT 158 Quad 2-Input Multiplexer Connection Diagrams Description The ’AC/'ACT158 is a high-speed quad 2-input multiplexer. It selects four bits of data from two sources using the common Select and Enable inputs. The four buffered outputs present the

AA13

Abstract: AA19 AC11 AC13 AD12
Contextual Info: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool

AA13

Abstract: AA19 AC11 AC13 AD12
Contextual Info: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool

AA13

Abstract: AA19 AC11 AC13 AD12
Contextual Info: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool

Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5

ORP 112

Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — — — — — — — fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay D3 D5

Contextual Info: ispLSI 3320 In-System Programmable High Density PLD Functional Block Diagram J0 Output Routing Pool ORP G3 F3 G2 G1 G0 F2 F1 F0 E3 D Q D Q H1 E2 OR Array D Q E1 H2 H3 D Q D Q OR Array Twin GLB E0 D Q D3 D Q D2 I1 D Q I2 D1 I3 D0 C3 Global Routing Pool

B272

Abstract: BC470
Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

B272

Abstract: 203d6
Contextual Info: ispLSI 3160 High Density Programmable Logic Features Functional Block Diagram E3 E2 E1 E0 A0 ORP OR Array ORP A2 A3 D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

B272

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

203d6

Abstract: B272
Contextual Info: ispLSI 3160 Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency — tpd = 7.5 ns Propagation Delay

B272

Contextual Info: ispLSI 3160 In-System Programmable High Density PLD Features Functional Block Diagram ORP E3 E2 E1 E0 A0 ORP OR Array A3 AND Array D Q D2 D Q D Q D Q OR Array D Q Twin GLB D1 ORP ORP A2 D3 D Q A1 • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — fmax = 125 MHz Maximum Operating Frequency

2128-80LT

Contextual Info: ® ispLSI and pLSI 2128 High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

STEL-2105

Abstract: 2105 LINEAR STEL-2110A STEL-2130A STEL-2130 2105 STEL-2100A receiver timing recovery discriminator integrat
Contextual Info: STEL-2105 Data Sheet STEL-2105 Digital Downconverter & Bit Synchronizer/QPSK Demodulator For Cable Applications R TABLE OF CONTENTS FEATURES AND BENEFITS . BLOCK DIAGRAM.

E2633

Abstract: 2128A Si 21 C28E
Contextual Info: ispLSI 2128/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay • IN-SYSTEM PROGRAMMABLE D0 C7 A1 C6 A2 A3 Logic Array A4 A5 D Q D Q D Q