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    32M-WORD Datasheets

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    Part ECAD Model Manufacturer Description Download Buy
    CD40105BF Texas Instruments CMOS 4-Bit-by-16-Word FIFO Register 16-CDIP -55 to 125 Visit Texas Instruments
    CD40105BF3A Texas Instruments CMOS 4-Bit-by-16-Word FIFO Register 16-CDIP -55 to 125 Visit Texas Instruments Buy
    CD40105BE Texas Instruments CMOS 4-Bit-by-16-Word FIFO Register 16-PDIP -55 to 125 Visit Texas Instruments Buy
    CD74HC40105M Texas Instruments High Speed CMOS Logic 4-Bit by 16-Word FIFO Register 16-SOIC -55 to 125 Visit Texas Instruments Buy
    CD74HCT40105E Texas Instruments High Speed CMOS Logic 4-Bit by 16-Word FIFO Register 16-PDIP -55 to 125 Visit Texas Instruments Buy
    CD74HCT40105M Texas Instruments High Speed CMOS Logic 4-Bit by 16-Word FIFO Register 16-SOIC -55 to 125 Visit Texas Instruments Buy

    32M-WORD Datasheets Context Search

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    MR27V3266D

    Abstract: No abstract text available
    Text: MR WORD CLK CKE CLK CE August , 1999 Revision 2.4 STO OE AMPX , /RAS DC / WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DC DQ5 VCCQ DC DQ6 VSSQ DC , VCC DQM NC /CAS /RAS /CS / WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DQ20 DQ5 , DQM="H"2 / WORD x32 x16 /WORDRead "H"=x32 "L"=x16 VCC 3.3V VSS , " DQ0-DQ15 / WORD x32 x16 / WORD "H"=x32 "L"=x16 STO="H"/WORDVSS


    Original     		PDF MR27V3266D MR27V3266D32MOTPOTPPROM 66MHzCAS 50MHzCAS 86-P-400-0 32MOTP 48DIP MR27V3266D32MOTPSTO 32MOTPEPROM MR27V3266D

    1999 - Not Available

    Abstract: No abstract text available
    Text: Read 25 mA (tCYCLE = 200 ns MAX.) ­ Word write 57 mA (MAX.) ­ Block erase 42 mA (MAX.) ­ Standby , blocking architecture for each bank ­ Two 4K- word boot blocks ­ Six 4K- word parameter blocks Stacked Chip 32M Flash Memory and 4M SRAM ­ Thirty-one 32K- word main blocks ­ Bottom boot location ­ Extended cycling capability ­ 100,000 block erase cycles ­ Enhanced automated suspend options ­ Word write suspend to read ­ Block erase suspend to word write ­ Block erase suspend to read · SRAM ­ Access time 85 ns


    Original     		PDF LRS1337 72-pin LCSP072-P-0811) 32K-word SMA99118

    1999 - MR27V3266D

    Abstract: ra1 cb
    Text: MR WORD CLK CKE CLK CE August , 1999 Revision 2.4 STO OE AMPX , /RAS DC / WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DC DQ5 VCCQ DC DQ6 VSSQ DC , VCC DQM NC /CAS /RAS /CS / WORD A12 A11 A10 A0 A1 A2 NC VCC NC DQ4 VSSQ DQ20 DQ5 , DQM="H"2 / WORD x32 x16 /WORDRead "H"=x32 "L"=x16 VCC 3.3V VSS , " DQ0-DQ15 / WORD x32 x16 / WORD "H"=x32 "L"=x16 STO="H"/WORDVSS


    Original     		PDF MR27V3266D MR27V3266D32MOTPOTPPROM 66MHzCAS 50MHzCAS 86-P-400-0 32MOTP 48DIP MR27V3266D32MOTPSTO 32MOTPEPROM MR27V3266D ra1 cb

    1998 - MR27V3266D

    Abstract: No abstract text available
    Text: electrically switched between 2,097,152 x16bit( word mode) and 1,048,576 x32bit(double word mode) by the state of the / WORD pin. The MR27V3266D supports high speed synchronous read operations using a single 3.3V , address Dual, electrically switchable configurations 2M x16( word mode) / 1M x32(double word mode) All , programming 10µs programming pulse per word allows high speed programming. 32M Synchronous OTP December , Controller MR WORD Data Outputs Selector Mode Register CLK Buffer CKE Program Mode


    Original     		PDF MR27V3266D MR27V3266D 32Mbit x16bit x32bit 66MHz 50MHz D-41460

    MR27V3266D

    Abstract: LA5A6
    Text: be electrically switched between 2,097,152 x16bit( word mode) and 1,048,576 x32bit(double word mode) by the state of the / WORD pin. The MR27V3266D supports high speed synchronous read operations using a , address - Dual, electrically switchable configurations 2M x16( word mode) /1M x32(double word mode) - , speed programming 10ns programming pulse per word allows high speed programming. December, 1998 , K9 i DC /OE /RAS /RAS i 19 (S3 i CLK DC DC ICS i •A) h/ i CKE DC / WORD / WORD i V1 (S


    OCR Scan     		PDF MR27V3266D MR27V3266D 32Mbit x16bit x32bit 66MHz 50MHz LA5A6

    Not Available

    Abstract: No abstract text available
    Text: organization 32 bit organization 70-PIN SSOP TOP VIEW ( Word mode: W = V|L) x f Ao IZ 1 · A iC 2 A2 IZ , -bit mask-programmable ROM organized as 2,097,152 x 16 bits ( Word mode) or 1,048,576 x 32 bits (Double Word mode). It is , W pin is set to be LOW in word mode, and data output (D31) when setto be HIGH in double word mode , WORD /DOUBLE WORD SWITCHOVER CIRCUIT GND 53BV32R00-2 Figure 2. LH53BV32R00 Block Diagram 2 , ( word /double word ) mode select input CE OE Vcc GND NC Chip enable input Output enable input Power


    OCR Scan     		PDF 16/1M 70-PIN 500-m LH53BV32R00 70SSOP SSOP70-P-500) LH53BV32R00 70-pin,

    1997 - Not Available

    Abstract: No abstract text available
    Text: LH53BV32R00 FEATURES · 2,097,152 × 16 bit organization ( Word mode: W = VIL) 1,048,576 × 32 bit organization (Double Word mode: W = VIH) · Access time: 120 ns (MAX.) Access time in page mode: 50 ns (MAX.) · , -bit mask-programmable ROM organized as 2,097,152 × 16 bits ( Word mode) or 1,048,576 × 32 bits (Double Word mode). It is , becomes LSB address input (A-1) when the W pin is set to be LOW in word mode, and data output (D31) when set to be HIGH in double word mode. 53BV32R00-1 Figure 1. Pin Connections 1 LH53BV32R00


    Original     		PDF LH53BV32R00 500-mil LH53BV32R00 32M-bit sili08] 70SSOP 70-pin, SSOP70-P-500) LH53BV32R00N

    1998 - MR27V3266D

    Abstract: No abstract text available
    Text: electrically switched between 2,097,152 x16bit( word mode) and 1,048,576 x32bit(double word mode) by the state of the / WORD pin. The MR27V3266D supports high speed synchronous read operations using a single 3.3V , address Dual, electrically switchable configurations 2M x16( word mode) / 1M x32(double word mode) All , programming 10µs programming pulse per word allows high speed programming. 32M Synchronous OTP April , Controller MR WORD Data Outputs Selector Mode Register CLK Buffer CKE Program Mode


    Original     		PDF MR27V3266D MR27V3266D 32Mbit x16bit x32bit 66MHz 50MHz D-41460

    1999 - MR27V3266D

    Abstract: No abstract text available
    Text: can be electrically switched between 2,097,152 x16bit( word mode) and 1,048,576 x32bit(double word mode) by the state of the / WORD pin. The MR27V3266D supports high speed synchronous read operations using , with multiplexed address Dual, electrically switchable configurations 2M x16( word mode) / 1M x32(double word mode) All inputs are sampled at the rising edge of the system clock High speed read , 10µs programming pulse per word allows high speed programming. 32M Synchronous OTP August , 1999


    Original     		PDF 50MHz. MR27V3266D

    1997 - Not Available

    Abstract: No abstract text available
    Text: LH53BV32900 FEATURES · 2,097,152 × 16 bit organization ( Word mode: W = VIL) 1,048,576 × 32 bit organization (Double Word mode: W = VIH) · Access time: 100 ns (MAX.) Access time in page mode: 30 ns (MAX.) · , ( Word mode) or 1,048,576 × 32 bits (Double Word mode). It is fabricated using silicon-gate CMOS process , W pin is set to be LOW in word mode, and data output (D31) when set to be HIGH in double word mode , ADDRESS DECODER ADDRESS BUFFER W 67 WORD /DOUBLE WORD SWITCHOVER CIRCUIT ADDRESS BUFFER


    Original     		PDF LH53BV32900 70-pin, 500-mil LH53BV32900 32M-bit 70SSOP SSOP70-P-500) LH53BV32900T

    1995 - 44-PIN

    Abstract: 48-PIN
    Text: organization ( Word mode) · Access time: 150 ns (MAX.) · Power consumption: Operating: 126 mW (MAX , -bit mask-programmable ROM organized as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits ( Word mode) that can be , / WORD SWITCHOVER CIRCUIT SENSE AMPLIFIER ADDRESS BUFFER 31 A-1 23 VCC 13 32 GND , ) Byte/ word mode switch 1 GND NOTE Ground Chip Enable input NC No connection NOTE , , and data output (D15) when set to be HIGH in word mode. 5-332 CMOS 32M Mask-Programmable ROM


    Original     		PDF LH53V32500 44-PIN 44-pin, 600-mil 48-pin, LH53V32500 32M-bit 48TSOP 48-PIN

    Not Available

    Abstract: No abstract text available
    Text: CMOS 3 2 M (2M x 16/1M x 32) MROM FEATURES · 2,097,152 x 16 bit organization ( Word mode: W = V,L ) 1,048,576 x 32 bit organization (Double Word mode: W = Vm) · Access time: 120 ns (MAX.) Access time , ) DESCRIPTION The LH53BV32R00 is a 32M-bit mask-programmable ROM organized as 2,097,152 x 16 bits ( Word mode) or 1,048,576 x 32 bits (Double Word mode). It is fabricated using silicon-gate CMOS process technol , _,) when the W pin is set to be LOW in word mode, and data output (D31) when set to be HIGH in double word


    OCR Scan     		PDF 16/1M 500-mil LH53BV32R00 32M-bit LH53BV32R00 70SSO SSOP70-P-500) 70-pin,

    Not Available

    Abstract: No abstract text available
    Text: CMOS 32M (2M x 16/1M x 32) MROM FEATURES · 2,097,152 x 16 bit organization ( Word mode: W = V|L) 1,048,576 x 32 bit organization (Double Word mode: W = Vm) · Access time: 100 ns (MAX.) Access time in , 32M-bit MROM organized as 2,097,152 x 16 bits ( Word mode) or 1,048,576 x 32 bits (Double Word mode). , LOW in word mode, and data output (D31) when set to be HIGH in double word mode. 53BV32900-1 , OE OE BUFFER W I WORD /DOUBLE WORD SWITCHOVER CIRCUIT ADDRESS BUFFER ADDRESS BUFFER


    OCR Scan     		PDF 16/1M 70-pin, 500-mil 70-PIN LH53BV32900 70SSOP SSOP70-P-500) LH53BV32900

    1999 - MR27V3266D

    Abstract: No abstract text available
    Text: switched between 2,097,152 x16bit( word mode) and 1,048,576 x32bit(double word mode) by the state of the / WORD pin. The MR27V3266D supports high speed synchronous read operations using a single 3.3V power , Dual, electrically switchable configurations 2M x16( word mode) / 1M x32(double word mode) All inputs , used. High speed programming 10µs programming pulse per word allows high speed programming. 32M , Sequence Controller MR WORD Data Outputs Selector Mode Register CLK Buffer CKE


    Original     		PDF MR27V3266D MR27V3266D 32Mbit x16bit x32bit 66MHz 50MHz.

    Not Available

    Abstract: No abstract text available
    Text: ,097,152 words x 16 bit organization ( Word mode) · Access time: 120 ns (MAX.) · Power consumption , ,097,152 x 16 bits ( Word mode) that can be selected by a BYTE input pin. It is fabricated using , TIMING GENERATOR SENSE AMPLIFIER OE C 14> OE BUFFER BYTE BYTE/ WORD SWITCHOVER CIRCUIT , NOTE ? Address input Data output Byte/ word mode switch Chip Enable input 1 1 1 OE V cc , , and data output (D15) when set to be HIGH in word mode. S H A R P » 3 LH 5332POO CMOS 32M


    OCR Scan     		PDF 44-pin, 600-mil 48-pin, LH5332P00 32M-bit 44-PIN LH5332P00 48TSOP

    1997 - D1133

    Abstract: No abstract text available
    Text: organization ( Word mode) · Access time: 150 ns (MAX.) · Power consumption: Operating: 126 mW (MAX.) Standby , -bit mask-programmable ROM organized as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits ( Word mode) that can be , BUFFER TIMING GENERATOR 15 D0 SENSE AMPLIFIER OE 14 OE BUFFER BYTE 33 BYTE/ WORD , PIN NAME NOTE A­1 ­ A20 D0 ­ D15 BYTE CE Address input Data output Byte/ word mode switch Chip , byte mode, and data output (D15) when set to be HIGH in word mode. 3 LH53V32500 CMOS 32M MROM


    Original     		PDF LH53V32500 44-pin, 600-mil 48-pin, LH53V32500 32M-bit 44-PIN 48TSOP D1133

    TB 1275 an

    Abstract: No abstract text available
    Text: bit organization ( Word mode) · Access time: 120 ns (MAX.) · Power consumption: Operating: 440 mW (MAX , -bit mask-programmable ROM organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits ( Word mode) that can be , Data output Byte/ word mode switch Chip Enable input 1 1 1 OË Output Enable input Power supply , ,) when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode , BUFFER BYTE M > BYTE/ WORD SWITCHOVER CIRCUIT NOTE: Pin numbers apply to the 48-pin TSOP (Type I


    OCR Scan     		PDF 44-pin, 600-mil 48-pin, 44-PIN 48TSOP 12x18 LH5332P00 TB 1275 an

    Not Available

    Abstract: No abstract text available
    Text: ,152 words x 16 bit organization ( Word mode) · Access time: 120 ns (MAX.) · Power consumption , ,097,152 x 16 bits ( Word mode) that can be selected by a BYTE input pin. It is fabricated using , <15) Dn OE BUFFER BYTE/ WORD SWITCHOVER CIRCUIT ADDRESS BUFFER 2 3 ) - ( 1 3 X 3 2 , mode, and data output (D 15 ) w hen set to be HIGH in word mode. SHARP < 1 T < CE Address input Data output Byte/ word mode switch Chip Enable input OE V cc GND O utput Enable input Power


    OCR Scan     		PDF 44-pin, 600-mil 48-pin, LH5332P00 32M-bit LH5332P00 44SOP OP044-P-0600)

    1995 - 44-PIN

    Abstract: 48-PIN
    Text: organization (Byte mode) 2,097,152 words × 16 bit organization ( Word mode) · Access time: 150 ns (MAX.) · , as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits ( Word mode) that can be selected by a BYTE , BUFFER BYTE 33 BYTE/ WORD SWITCHOVER CIRCUIT SENSE AMPLIFIER ADDRESS BUFFER 31 A , Power supply (+5 V) Byte/ word mode switch 1 GND Ground Chip Enable input NOTE: 1. The , output (D15) when set to be HIGH in word mode. 5-350 NOTE CMOS 32M Mask-Programmable ROM


    Original     		PDF LH5332500B 44-pin, 600-mil 48-pin, LH5332500B 32M-bit 44-PIN 48TSOP 48-PIN

    a5c capacitor

    Abstract: TM 1218 48-PIN A17C LH5332500BN TSOP048-P-1218 12X18 SAA 1220
    Text: bit organization (Byte mode) 2,097,152 words x 16 bit organization ( Word mode) • Access time: 150 , -bit mask-programmable ROM organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits ( Word mode) that can be , LH5332500B CMOS 32M Mask-Programmable ROM BYTE MEMORY MATRIX (4,194,304 x 8) (2,097,152 x 16) BYTE/ WORD , output 1 BYTE Byte/ word mode switch 1 CE Chip Enable input SIGNAL PIN NAME NOTE OÊ Output Enable , -0 when the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode


    OCR Scan     		PDF LH5332500B 44-pin, 600-mil 48-pin, 12x18 LH5332500B 32M-bit 44-pin 48tsop a5c capacitor TM 1218 48-PIN A17C LH5332500BN TSOP048-P-1218 SAA 1220

    Not Available

    Abstract: No abstract text available
    Text: ) 2,097,152 words x 16 bit organization ( Word mode) · Access time: 150 ns (MAX.) · Power consumption , 32M-bit mask-programmable ROM organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits ( Word , NAM E NOTE SIG N A L PIN NAM E NOTE ? Address input Data output Byte/ word mode switch Chip , pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. S H A R , ,152x 16) CE BUFFER TIMING GENERATOR SENSE AMPLIFIER BYTE BYTE/ WORD SWITCHOVER CIRCUIT


    OCR Scan     		PDF 44-pin, 600-mil 48-pin, LH5332500B 48TSOP TSOP048-P-1218) LH5332500B

    Not Available

    Abstract: No abstract text available
    Text: organization ( Word mode) · Access time: 150 ns (MAX.) · Power consumption: Operating: 126 mW (MAX.) Standby , organized as 4,194,304 x 8 bits (Byte mode) or 2,097,152 x 16 bits ( Word mode) that can be selected by a , NAM E NOTE SIG N A L PIN NAM E NOTE ? Address input Data output Byte/ word mode switch Chip , the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode , BUFFER B YTE © - BYTE/ WORD SWITCHOVER CIRCUIT NOTE : Pin numbers apply to the 48-pin TSOP (Type


    OCR Scan     		PDF LH53V32500 44-pin, 600-mil 48-pin, 48TSOP TSOP048-P-1218)

    2010 - EDJ2116DASE

    Abstract: EDE2116ACBG ECM220ACBCN ELPIDA EDJ2116DASE EDJ1108DBSE EDE1032AGBG GDDR5 EDX1032BASE DDR3-1333H EDE1116AGBG
    Text: .8 Selection Guide J1610E30 (Ver.3.0) 3 DRAM 1. DDR3 SDRAM Density Organization ( word x , 240-pin Registered DIMM Organization ( word x bit) Module Ranks Grade (CL-tRCD-tRP) Part , Density Organization ( word x bit) Module Ranks Grade (CL-tRCD-tRP) 2GB 256M x 64 2 , Density Organization ( word x bit) Module Ranks Grade (CL-tRCD-tRP) 4GB 512M x 64 2 , Organization ( word x bit) Module Ranks 2Gbit 128M x 16 8 DDR2-1066(7-7-7) DDR2-800(5-5-5


    Original     		PDF J1610E30 240-pin EDU1032AABG 136-FBGA M01J0706 TEL033281-1563 TEL066390-8727 EDJ2116DASE EDE2116ACBG ECM220ACBCN ELPIDA EDJ2116DASE EDJ1108DBSE EDE1032AGBG GDDR5 EDX1032BASE DDR3-1333H EDE1116AGBG

    1995 - LH5332P00N

    Abstract: 44-PIN 48-PIN
    Text: organization (Byte mode) 2,097,152 words × 16 bit organization ( Word mode) · Access time: 120 ns (MAX.) · , -bit mask-programmable ROM organized as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits ( Word mode) that can be , BUFFER OE 14 TIMING GENERATOR 15 D0 OE BUFFER BYTE 33 BYTE/ WORD SWITCHOVER CIRCUIT , Enable input Data output 1 VCC Power supply (+5 V) Byte/ word mode switch 1 GND , the BYTE pin is set to be LOW in byte mode, and data output (D15) when set to be HIGH in word mode


    Original     		PDF LH5332P00 44-pin, 600-mil 48-pin, 44-PIN 48TSOP LH5332P00N 48-PIN

    1997 - Not Available

    Abstract: No abstract text available
    Text: organization ( Word mode) · Access time: 120 ns (MAX.) · Power consumption: Operating: 440 mW (MAX.) Standby , 32M-bit mask-programmable ROM organized as 4,194,304 × 8 bits (Byte mode) or 2,097,152 × 16 bits ( Word , OE BUFFER BYTE 33 BYTE/ WORD SWITCHOVER CIRCUIT ADDRESS BUFFER 31 A-1 NOTE: Pin numbers , output Byte/ word mode switch Chip Enable input 1 1 1 OE VCC GND Output Enable input Power supply , be LOW in byte mode, and data output (D15) when set to be HIGH in word mode. 3 LH5332P00


    Original     		PDF LH5332P00 44-pin, 600-mil 48-pin, LH5332P00 32M-bit 44-PIN 48TSOP
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