32-BIT MICROPROCESSOR PIPELINE ARCHITECTURE Search Results

T9000

Abstract: STC104 IMST900-F20S IMST9000 inmos T9000 IMS processor inmos transputer reference manual
Contextual Info: IMS T9000 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H Workspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit

Contextual Info: 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H W orkspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit H 16 Kbyte instruction and data cache

T9000

Abstract: STC104 STC104s
Contextual Info: 32 BIT MICROPROCESSOR FEATURES H Pipelined superscalar micro-architecture Central Processing Unit H Workspace cache 32 bit Integer Unit H Programmable memory interface 7 Stage Pipeline H 4 Gbyte physical address space 64 bit Floating Point Unit H 16 Kbyte instruction and data cache

RC32300

Contextual Info: RISController Embedded 32-bit Microprocessor, based on RISCore32300 Features • • High-performance embedded RISController™ micro­ processor, based on IDT RC32300™ 32-bit CPU core - Based on MIPS-II RISC architecture with enhance­ ments - Scalar 5-stage pipeline minimizes branch and load

RC3041

Abstract: RC32364 RC4640 RC4650
Contextual Info: RC32364 RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300 HDWXU WXUHV ◆ – Variable number of locked entries – No performance penalty for address translation ◆ Flexible bus interface allows simple, low-cost designs – Bus interface runs at a fraction of pipeline rate

bta 137

Contextual Info: RC32364 RISControllerTM Embedded 32-bit Microprocessor, based on RISCore32300    ◆ – Variable number of locked entries – No performance penalty for address translation ◆ Flexible bus interface allows simple, low-cost designs – Bus interface runs at a fraction of pipeline rate

Contextual Info:
 
       
 


 ◆ ◆ TM High-performance embedded RISController microprocessor, based on IDT RISCore32300TM 32-bit CPU core Based on MIPS-II RISC architecture with enhancements Scalar 5-stage pipeline minimizes branch and load

Intel i860

Contextual Info: INTEL CORP UP/PRPHLS bflE » • 4ñ2bl7S Dia^flSb in te i i860 XR 64-BIT MICROPROCESSOR ■ Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per

FGT 313

Contextual Info: in te i ¡860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

Contextual Info: in te * MILITARY i860 64-BIT MICROPROCESSOR Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for

Contextual Info: i860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design — 25/33.3/40 MHz Clock Rates

00FF

Abstract: 06FFFFFF cache of translation lookaside buffer content
Contextual Info: Chapter 3 Memory Management Unit / Caches 3.1 MMU OVERVIEW The MMU, which conforms to the SPARC Reference MMU Architecture, provides three primary functions: • Performs address translations from virtual addresses of each running process to physical addresses in physical

intel i860

Abstract: A80860XR-40 pbit 2180 a80860xr-33 A80860XR40 TE 2197 transistor 8550 sad intel I860 processor pin diagram of XR 2206 i860 64-Bit Microprocessor Performance Brief
Contextual Info: i860 XR 64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock ' — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design — 25/33.3/40 MHz Clock Rates

00A75

Abstract: INTEL Core i7 860 J 80222 lm 6358 J1 3009-2 271121 Texture mapping CC1105 Intel i860
Contextual Info: P K H IL D fiflD M M V MILITARY i860 XR 32/64-BIT MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction per Clock — Up to Two Floating-Point Results per Clock ■ High Performance Design

Contextual Info: r a iO M O G O M V Military ì860tm 64-Bit M icro p ro cesso r • Compatible with Industry Standards — ANSI/IEEE Standard 754-1985 for Binary Floating-Point Arithmetic — 386 /j 486TM Microprocessor Data Formats and Page Table Entries ■ Parallel Architecture that Supports Up

CISC dan RISC

Abstract: PDP-11 alpha 600 manual instruction 21164a
Contextual Info: Internal Organization of the Alpha 21164, a 300-MHz 64-bit Quad-issue CMOS RISC Microprocessor A new CMOS microprocessor, the Alpha 21164, reaches 1,200 mips/600 MFLOPS peak performance . This new implementation of the Alpha architecture achieves SPECint92/SPECfp92

ba 6414 fs

Abstract: RTL 2832 A80860XP i860Xp 80860XR 80860XP equivalent of transistor tt 2148 transistor x 313 ca 361 e ic 82490XP
Contextual Info: intei I860 XP MICROPROCESSOR • Parallel Architecture that Supports Up to Three Operations per Clock — One Integer or Control Instruction — Up to Two Floating-Point Results ■ High Performance Design — 40/50 MHz Clock Rate — 100 Peak Single Precision MFLOPS

alpha date code System

Abstract: branch conditional unconditional instruction
Contextual Info: Digital Semiconductor Alpha 21164 Microprocessor Product Brief March 1995 Description The Alpha 21164 microprocessor is a high-performance implementation of Digital’s Alpha architecture designed for application servers and high-performance clients. It has a superscalar design capable of issuing four instructions every clock

32 bit carry select adder code

Abstract: MPC603E MPC603e FPU 32-bit microprocessor architecture detail of half adder ic microprocessor architecture programming Power motorola microprocessor 32 bit SR15
Contextual Info: Freescale Semiconductor, Inc. Technical Summary MPC603E/D Rev. 2 11/2001 Freescale Semiconductor, Inc. MPC603e RISC Microprocessor Technical Summary This document provides an overview of features for the MPC603e microprocessor and PowerPC architecture, and information about how the MPC603e implementation complies

16 BIT ALU design structural

Contextual Info: Chapter 2 TurboSPARC Architecture 2.1 INTEGER UNIT AND FLOATING POINT CONTROLLER The integer unit IU and floating point control (FPC) are merged into a 9-stage pipeline. Below are some of the features of the IUFPC. • 9 stage instruction pipeline. • No branch folding. Branch instructions (taken/non-taken) execute in one cycle.

SR15

Contextual Info: Technical Summary MPC603E/D Rev. 2 11/2001 MPC603e RISC Microprocessor Technical Summary This document provides an overview of features for the MPC603e microprocessor and PowerPC architecture, and information about how the MPC603e implementation complies with the architectural definitions. Note that the MPC603e microprocessor is implemented in

Contextual Info: SÖE D ADVANCED MICRO DEVICES • 02S7S25 GQ332G^ 1 _ B g g g g g g T i j p -n-H L. _ Cl Advanced Micro Devices Am29005 Low-Cost Streamlined Instruction Microprocessor DISTINCTIVE CHARACTERISTICS ■ ■ ■ ■ ■ Full 32-blt, three-bus architecture

prom 123

Abstract: C21x GF9101 IN17 IN18 IN19
Contextual Info: MultiGEN GF9101 High Performance Multirate Digital Filter DATA SHEET DESCRIPTION • highly optimized & flexible architecture for multirate FIR filtering applications The GF9101 is a high performance multirate digital filter which can be programmed to implement a wide range of

XC1736

Abstract: GF9101 IN17 IN18 IN19 pipelined adder
Contextual Info: 0XOWLGEN GF9101 High Performance Multirate Digital Filter DATA SHEET • highly optimized & flexible architecture for multirate FIR filtering applications The GF9101 is a high performance multirate digital filter which can be programmed to implement a wide range of