3 PHASE FULL CONTROLED BRIDGE Search Results

xf4f

Contextual Info: LT4420 Dual 32-Tap Transversal FIR Filter DEVICES INCORPORATED Advance Information FEATURES 165 MHz Max Data Rate 330 MHz Max Core Clock Rate 16-bit Data and Coefficients Paths 64-Tap FIR Filter, Cascadable for More Filter Taps 512 Coefficients per Tap Multiple Operating Modes: Dual Filter, Single Filter,

s11 stopping compound

Abstract: as15 4804B
Contextual Info: LT4420 LT4420 DEVICES INCORPORATED DEVICES INCORPORATED FEATURES ❑ ❑ ❑ ❑ 155 MHz Max Data Rate 312 MHz Max Core Clock Rate 16-bit Data and Coefficients Paths 64-Tap FIR Filter, Cascadable for More Filter Taps Dual 32-Tap Transversal FIR Filter DESCRIPTION

Contextual Info: TB62206FG TOSHIBA BiCD Processor IC Silicon Monolithic TB62206FG BiCD PWM 2−Phase Bipolar Stepping Motor Driver The TB62206FG is designed to drive a 2−phase bipolar setpping motor. With BiCD process technology, this device enables output withstand voltage of 40 V and maximum current

DP83840

Abstract: GT-48002 "Spanning Tree" BUT15
Contextual Info: Switched Fast Ethernet Controller Galileo Technology TM GT- 48002 Preliminary Rev. 1.1 October 2, 1996 NOTE: Always contact Galileo Technology for possible updates before starting a design. FEATURES • Member of GalNetTM Architecture Family • Ideal uplink/server connect for the 10 Mbps GT-48001

0DG02

Abstract: "Spanning Tree" BUT15
Contextual Info: Switched Fast Ethernet Controller H j Galileo Technology GT- 48002 Preliminary Rev. 1.1 October 2 , 1996 NOTE: Always contact Galileo Technology for possible updates before startina a aesiqn. FEATURES Member of GalNet™ Architecture Family Ideal uplink/setver connect for the 10 Mbps GT-48001

Triac/TRIAC TAG 92

Abstract: TRIAC TAG 425 600 TRIAC TAG 280 600 tag 453 triac triac tag 425 400 TRIAC TAG 92 transistor ac51 EN60669-2-1 TAG 453 280 800 TRIAC TAG 90
Contextual Info: SIMM Series Input Modules * 6.2 mm wide and 65 mm deep * DIN Rail mounted * LED input status indicator * Bridges enable quick linking of common voltage * Identification zone on front face * IP20 Part numbers 84145061 84145062 84145064 84145066 84145071 24Vac/dc

zo405mf

Abstract: triac ZO405MF BTA16-600b application motor control SCR tyn612 BTB16-600bw application motor control BTa16-600bw application motor control BTA16-600B heating control diagram 220v dimmer light bt139 bta41-600b application BTA40-700B
Contextual Info: Thyristors and AC switches from SCRs and TRIACS to innovative devices USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. STMicroelectronics PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF STMicroelectronics. As used herein:

TR4 TRANSISTOR SMD MARKING CODE

Contextual Info: Relays subminiature miniature industrial interface installation programmable time monitoring plug-in sockets www.relpol.com.pl 2014 - 2015 Automation is our passion The leading position of the manufacturer of electromagnetic relays in Europe provides for Relpol’s presence

Contextual Info: S lI l^ C L P C 4 7 B 2 7 x STANDARD MICROSYSTEMS CORPORATION 100 Pin Enhanced Super I/O Controller with LPC Interface for Consumer Applications FEATURES 3.3 Volt Operation 5 Volt Tolerant Fan Control Fan Speed Control Outputs Fan Tachometer Inputs Programmable Wake-up Event Interface

DIP28

Abstract: PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P STLC5464 STLC5465
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE

AT697

Abstract: AT697E 86MIPS ASR-24
Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache

Contextual Info: GT-96010 Remote Access Coprocessor Product Pre vie w Revision 0.59 i.p. 5/28/97 Please contact Galileo Technology for possible updates before finalizing a design. FEATURES Integrated serial communications controller and system core logic device - Direct interface to i960 Jx family of CPUs

Edd 44

Abstract: audio transformer GCI DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P STLC5464 STLC5465
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE

Edd 44

Abstract: m51x DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P STLC5464 STLC5465
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PRELIMINARY DATA GENERAL FEATURES SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS MEETS OR EXCEEDS ETSI EUROPEAN STANDARD SINGLE 5V SUPPLY DIP28 AND PLCC44 PACKAGE

AT697

Abstract: 4226G AT697F D3/220 DC Kit AT697E MQFP-256 atmel edac D10136
Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache

AT697

Abstract: AT697F AT697E 4426D ASR16
Contextual Info: Features • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data Cache

32KHZ

Abstract: 82077AA MPU-401 PC99
Contextual Info: LPC47B27x 100 Pin Enhanced Super I/O Controller with LPC Interface FEATURES • • • • • • • • • • • • • • • • 3.3 Volt Operation, 5 Volt Tolerant LPC Interface Fan Control Fan Speed Control Outputs 2 Fan Tachometer Inputs (2)

transistor J1y

Abstract: j2y transistor
Contextual Info: LPC47M192 LPC Super I/O with Hardware Monitoring Block FEATURES 3.3 Volt Operation SIO Block is 5 Volt Tolerant LPC Interface ACPI 1.0/2.0 Compliant Fan Control Fan Speed Control Outputs (2) Fan Tachometer Inputs (2) Programmable Wake-up Event Interface

j2y transistor

Abstract: GP 809 DIODE transistor J1y 82077AA LPC47M152-NC LPC47M157-NC MPU-401 PC99
Contextual Info: LPC47M15x PRELIMINARY LPC Super I/O with Hardware Monitoring Block FEATURES 3.3 Volt Operation SIO Block is 5 Volt Tolerant LPC Interface ACPI 1.0 Compliant Fan Control Fan Speed Control Outputs (2) Fan Tachometer Inputs (2) Programmable Wake-up Event Interface

transistor cd 4400

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dmo 365 r

Abstract: RF MODULE CIRCUIT DIAGRAM dect Edd 44 NT 101 DIP28 PLCC44 ST5451 STLC5412 STLC5412FN STLC5412P
Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED W ITH DECT MODE PRELIMINARY DATA GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN STANDARD ■ SINGLE 5V SUPPLY . DIP28 AND PLCC44 PACKAGE

Contextual Info: / T T SGS-IHOMSON * l i . M g[]MI[LI(§Ij»[](§S STLC5412 2B1Q U INTERFACE DEVICE ENHANCED W ITH DECT M ODE PR ELIM IN A R Y DATA G EN ER AL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN

Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED WITH DECT MODE PR E LIM IN A R Y DATA GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN STANDARD ■ SINGLE 5V SUPPLY

dmo 365 rn

Contextual Info: STLC5412 2B1Q U INTERFACE DEVICE ENHANCED W ITH DECT MODE PRELIMINARY DATA GENERAL FEATURES • SINGLE CHIP 2B1Q LINE CODE TRANSCEIVER ■ SUITABLE FOR ISDN, PAIR GAIN AND DECT APPLICATIONS ■ MEETS OR EXCEEDS ETSI EUROPEAN STANDARD ■ SINGLE 5V SUPPLY ■ DIP28 AND PLCC44 PACKAGE