3 INPUT OR GATE Search Results

Contextual Info: Data sheet acquired from Harris Semiconductor SCHS056B – Revised February 2003 CD4071B CD4072B CD4075B Quad 2-Input Dual 4-Input Triple 3-Input OR OR OR Gate Gate Gate H CD4071B, CD4072B, and CD4075B OR gates provide the system designer with direct implementation of the positive-logic OR

751A-02

Abstract: 74f64 motorola
Contextual Info: MC54/74F64 4-2-3-2-INPUT AND-OR-INVERT GATE 4-2-3-2-INPUT AND-OR-INVERT GATE FAST SCHOTTKY TTL VCC 14 13 12 11 10 9 8 J SUFFIX CERAMIC CASE 632-08 1 2 3 4 5 6 14 7 1 GND N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION

Contextual Info: H D 10117 Dual 2-wide 2-3-input OR-AND/OR-Af* P-INVERT Gates The E input (pin 9 is the common input o f dual, The H D 10117 is designed for use as a data control of digital Multiplexer, data distribution and etc. gates. I PIN ARRANGEMENT (Top View) I DC CHARACTERISTICS (V£ e = - 5 . 2 V ,

4-DIGIT counter with 7-SEGMENT DISPLAY

Abstract: binary to hex led display decoder TC5000 tc5067 IC451 IC-451 tc4036 TC5066 TC4012 Multivibrator 555
Contextual Info: TC4000 Series PAGE FUNCTION PRODUCT NAME TC4000BP DUAL 3 INPUT NOR GATE PLUS INVERTER 75 TC4001BP/BF/BFN QUAD 2 INPUT N OR GATE 80 TC4001UBP QUAD 2 INPUT NOR GATE 83 TC4002BP/BF DUAL 4 INPUT NOR GATE 80 18-STAGE STATIC SHIFT REGISTER V ' ' 86 1/ "TC4006BP

Contextual Info: TOSHIBA TC74HC4075AP/AF TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC TC74HC4075AP, TC74HC4075AF TRIPLE 3 -IN P U T OR GATE The TC74HC4075A is a high speed CMOS 3 - INPUT OR GATE fabricated with silicon gate C2MOS technology. It achieves the high speed operation similar to equivalent

SOP20

Abstract: SOL20 DIP20 DIP-20
Contextual Info: BiCMOS Standard Logics TD74BC Series A4 Typo No. Package Function TD74BC00P Quad 2-Input NAND Gate DIP14 TD74BC08P Quad 2-Input AND Gate DIP14 TD74BC32P Quad 2-Input OR Gate DIP14 TD74BC230P/F/FW Octal Bus Butter/Inverting and Non-lnvertlng/3-state DIP20/SOP20/SOL20

Contextual Info: SN74LVC1G332 www.ti.com SCES489E – SEPTEMBER 2003 – REVISED DECEMBER 2013 Single 3-Input Positive-OR Gate Check for Samples: SN74LVC1G332 FEATURES DESCRIPTION • The SN74LVC1G332 device performs the Boolean Y + A B ) C or Y + A • B • C function

Contextual Info: SN54F51, SN74F51 DUAL 2-WIDE 2-INPUT, 2-WIDE 3-INPUT AND-OR-INVERT GATES SDFS092 - JANUARY 1989 - REVISED OCTOBER 1993 • Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs SN54F51 . . . J PACKAGE

Contextual Info: SN54LV32A, SN74LV32A QUADRUPLE 2-INPUT POSITIVE-OR GATES SCLS385G – SEPTEMBER 1997 – REVISED OCTOBER 2002 SN54LV32A . . . J OR W PACKAGE SN74LV32A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 4B 4A 4Y 3B 3A 3Y 1B 1Y

LV10A

Contextual Info: SN54LV10A, SN74LV10A TRIPLE 3-INPUT POSITIVE-NAND GATE SCES338B – SEPTEMBER 2000 – REVISED DECEMBER 2000 D D D D SN54LV10A . . . J OR W PACKAGE SN74LV10A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

12-INPUT

Contextual Info: TYPES SN54S134, SN74S134 12-INPUT POSITIVE-NAND GATES WITH 3-STATE OUTPUTS R E V IS E D D E C E M B E R 1983 Package Options Include Both Plastic and Ceramic Chip Carriers in Addition to Plastic and Ceramic DIPs S N 5 4 S 1 3 4 . . . J OR W PACKAGE S N 7 4 S 1 3 4 . . . D , J OR N PACKA GE

SN54136

Contextual Info: TYPES SN54136, SN54LS136, SN74136, SN74LS136 QUADRUPLE 2-INPUT EXCLUSIVE-OR GATES WITH OPEN-COLLECTOR OUTPUTS D E C E M B E R 1 9 7 2 -R E V IS E D D E C E M B E R 1983 S N 5 4 1 3 6 . S N 54 L S 1 3 6 . . . J OR W PACKAGE F U N C T IO N T A B L E H S N 7 4 1 3 6 . . . J OR N PACKAGE

DL122

Abstract: MC10H123
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA Triple 4-3-3-Input Bus Driver MC10H123 The MC10H123 is a triple 4–3–3–Input Bus Driver. The MC10H123 consists of three NOR gates designed for bus driving applications on card or between cards. Output low logic levels are specified with

K12D

Contextual Info: SN54S134, SN74S134 12-INPUT POSITIVE NANO GATES WITH 3-STATE OUTPUTS DECEMBER 1983 - REVISED MARCH 19B8 Package Options Include Plastic "Sm all Outline" Packages, Ceramic Chip Carriers and Flat Packages, and Plastic and Ceramic DIPs S N 5 4 S 1 3 4 . . . J OR W PACKAGE

s433

Abstract: 74LS33 IC 7433
Contextual Info: SN 5433, SN 54LS33, SN 7433, SN 74 LS3 3 QUADRUPLE 2 INPUT POSITIVE-NOR BUFFERS WITH OPEN COLLECTOR OUTPUTS DECEMBER 1983-REVISED MARCH 19B8 S N 5 4 3 3 , S N 5 4 L S 3 3 . . J OR W PAC KA G E S N 7433 . . N P AC KA G E SN 74LS33 . . D OR N P AC KA G E TO P V IE W

Contextual Info: SN54LVC02A, SN74LVC02A QUADRUPLE 2-INPUT POSITIVE-NOR GATES SCAS280I – JANUARY 1993 – REVISED OCTOBER 1998 D D D D D SN54LVC02A . . . J OR W PACKAGE SN74LVC02A . . . D, DB, OR PW PACKAGE TOP VIEW 1Y 1A 1B 2Y 2A 2B GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8

Contextual Info: SN54F11, SN74F11 TRIPLE 3-INPUT POSITIVE-ANO GATES D2932, MARCH 1987-REVISED JANUARY 1989 • Package Options Include Plastic "Small Outline" Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mll DIPs SN64F11 . . . J PACKAGE SN74F11 . . . D OR N PACKAGE

Contextual Info: 54ACT11010, 74ACT11010 TRIPLE 3-INPUT POSITIVE-NAND GATES T0049— 2957, JU LY 1967— REVISED MARCH 1990 54ACT11010 . . . J PACKAGE 74ACT11010 . . . O OR N PACKAGE • Inputs are TTL-Voltage Compatible • Flow-Through Architecture to Optimize PCB Layout

Contextual Info: SN54F27, SN74F27 TRIPLE 3-INPUT POSITIVE-NOR GATES SDFS042A – MARCH 1987 – REVISED OCTOBER 1993 • SN54F27 . . . J PACKAGE SN74F27 . . . D OR N PACKAGE TOP VIEW Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, and Standard Plastic and Ceramic

DL122

Abstract: MC10212
Contextual Info: MOTOROLA SEMICONDUCTOR TECHNICAL DATA High Speed Dual 3-Input/ 3-Output OR/NOR Gate MC10212 The MC10212 is designed to drive up to six transmission lines simul– taneously. The multiple outputs of this device also allow the wire “OR”–ing of several levels of gating for minimization of gate and package count.

Contextual Info: H D 10 121 -4-w ide OR-AND/OR-AND-INVERT Gate • P IN ARRANGEMENT I'ccs K J H G E T a = - 3 0 - + 8G°C ■ D C C H A R A C TE R IS TIC S KE£= - 5 . 2 V , Ite m S u p p ly C u r r e n t T e s t C on d itio n Sy m b o l F input Input C u r r e n t

M3D2271

Contextual Info: 37E 4 3 D 2 2 7 1 005fei0cifl 2 IHAS H A RR IS S E M I C O N D S E CT OR SWITCHING CHARACTERISTICS: AC Series; CHARACTERISTICS Propagation Delay Input to Output Power Dissipation Capacitance InputCapacitance t„ ti CH ARACTERISTICS Propagation Delay Input to Output

Contextual Info: SN54S64, SN54S65, SN74S64, SN74S65 4-2-3-2 INPUT AND-OR-INVERT GATES SDLS205 – DECEMBER 1983 – REVISED MARCH 1988 Copyright  1988, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments

C4075

Abstract: SN 74HC4075 N
Contextual Info: SN54HC4075, SN74HC4075 TRIPLE 3-INPUT OR GATES D 2 6 8 4 , DECEMBER 1 9 8 2 -R E V IS E D SEPTEMBER 1987 SN54HC4075 . J PACKAGE S N 7 4 H C 4 0 7 5 . . . D OR N P A C K A G E Package Options include Plastic "S m a ll O u tline " Packages, Ceram ic Chip Carriers,