2CY7C1329 Search Results
2CY7C1329 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
CY7C1335Contextual Info: aven’t re CY7C1335 32K x 32 Synchronous-Pipelined Cache RAM All synchronous inputs pass through input registers controlled by the rising edge of the clock. All data outputs pass through output registers controlled by the rising edge of the clock. Maximum access delay from the clock rise is 4.2 ns 133-MHz |
Original |
CY7C1335 133-MHz 2CY7C1329 100-MHz 133-MHz CY7C1335 |