281GHZ Search Results

281GHZ Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: NONLINEAR MODEL NE33200 SCHEMATIC LG 0.19 RG CDG 0.16 0.04 GATE GGS 1E-5 RD 0.24 LD 0.2 DRAIN CGS 0.22 CDC 0.065 RDS g t f= 281GHz RI 0.52 CDS 0.05 RS 0.19 LS 0.03 SOURCE BIAS DEPENDENT MODEL PARAMETERS Parameters 2 V, 10 mA 2 V, 20 mA g 73 mS 96 mS t 2.5 pSec	Original	281GHz NE33200 24-Hour	PDF
NE33284AS Abstract: NE33284A NE33284A-SL NE33284A-T1 MODEL 536 Contextual Info: SUPER LOW NOISE HJ FET • VERY LOW NOISE FIGURE: 0.8 dB typical at 12 GHz • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm • LOW COST METAL/CERAMIC PACKAGE • TAPE & REEL PACKAGING OPTION AVAILABLE DESCRIPTION Noise Figure, NF dB • HIGH ASSOCIATED GAIN:	Original	NE33284A 24-Hour NE33284AS NE33284A-SL NE33284A-T1 MODEL 536	PDF
GM 90 562 573 Abstract: NE33200 NE33200M NE33200N Contextual Info: SUPER LOW NOISE HJ FET FEATURES NE33200 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to	Original	NE33200 NE33200 24-Hour GM 90 562 573 NE33200M NE33200N	PDF
NE33200 Abstract: NE33200M NE33200N Contextual Info: SUPER LOW NOISE HJ FET FEATURES NE33200 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to	Original	NE33200 NE33200 24-Hour NE33200M NE33200N	PDF
NE33284A Abstract: NE33284AS NE33284A-SL NE33284A-T1 Contextual Info: SUPER LOW NOISE HJ FET • VERY LOW NOISE FIGURE: 0.8 dB typical at 12 GHz • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm • LOW COST METAL/CERAMIC PACKAGE • TAPE & REEL PACKAGING OPTION AVAILABLE DESCRIPTION Noise Figure, NF dB • HIGH ASSOCIATED GAIN:	Original	NE33284A 24-Hour NE33284AS NE33284A-SL NE33284A-T1	PDF
Contextual Info: SUPER LOW NOISE HJ FET FEATURES NE33200 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to	Original	NE33200 NE33200 24-Hour	PDF
Contextual Info: SUPER LOW NOISE HJ FET FEATURES NE33200 NOISE FIGURE & ASSOCIATED GAIN vs. FREQUENCY VDS = 2 V, IDS = 10 mA • GATE LENGTH: 0.3 µm • GATE WIDTH: 280 µm DESCRIPTION The NE33200 is a Hetero-Junction FET chip that utilizes the junction between Si-doped AlGaAs and undoped InGaAs to	Original	NE33200 NE33200 24-Hour	PDF