259 DECODER Search Results

74hctls

Contextual Info: Z y tre x _ %%%&259 February 1985 8-Bit Addressable Latches OBJECTIVE SPECIFICATIONS Features Description • 8-Bit parallel-out storage register performs serial-to-parallel conversion with storage The '259 is a high-speed addressable latch designed for

54LS259

Abstract: 74LS259 DM54LS259J DM74LS259N DM74LS259WM J16A M16B N16A
Contextual Info: DM54LS259/DM74LS259 National Semiconductor Corporation D M 5 4L S 259/D M 74L S 259 8-B it A d dressable Latches General Description Features These 8-bit addressable latches are designed for general purpose storage applications in digital systems. Specific

hdmi h.265

Contextual Info: Stradis HDM850+ HEVC/H.265 Professional Decoder V I D E O I N N O VAT I O N S TECHNICAL SPECIFICATIONS HEVC/H.265 H.264 MPEG-1/2 HDM850+ VIDEO OUTPUTS Digital HD / SD-SDI up to 3Gb/s /1080p60 SMPTE 259, 292, 424,425-A HDMI 1.3 Secondary SD-SDI (SMPTE 259) for simultaneous HD & SD playback

74LS259PC

Contextual Info: 259 54LS/74LS259 CONNECTION DIAGRAM PINOUT A OH I I 0> 8-BIT ADDRESSABLE LATCH DESCRIPTION — The '259 is a high speed 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a multi­ functional device capable of storing single line data in eight addressable

Contextual Info: SN54HC259, SN74HC259 8 BIT ADDRESSABLE LATCHES D 26S 4. DECEMBER 1 9 8 2 -flE V IS E D SEPTEMBER 1987 SN54H C 259 SN74H C 259 8-Bit Parallel-Out Storage Register Performs Ssrial-to Parallel Conversion with Storage J P AC KAG E D OR N P AC KAG E ITO P VIE W

Contextual Info: SbE ]> • 7 ^ 5 ^ 5 37 00H00^3 QflO M S G T H Æ 7 *7 # S C S -T H O M S O N G * [i3 » [i(g T O * S M 54H C 259 M 74H C 259 S G S-THOMSON 8 BIT ADDRESSABLE LATCH ■ HIGH SPEED tpD = 13 ns (TYP.) at V c c = 5V ■ LOW POWER DISSIPATION Ice = 4 ttA (MAX.) at Ta = 25°C

74AHCT

Contextual Info: Zytrex ZXS4AHCT ZX74AHCT 259 8-Bit Addressable Latches February 1985 OBJECTIVE SPECIFICATIONS Features Description • 8-Bit parallel-out storage register performs serial-to-parallel conversion with storage The ’259 is a high-speed addressable latch designed for

Contextual Info: MT8808AE Linear ICs Crosspoint Switch Circuit status Military/High-RelN Nom. Supp V 10 Minimum Operating Temp (øC)-40 Maximum Operating Temp (øC)85 Package StyleDIP Mounting StyleT Pinout Equivalence Code28-259 # Pins28 Ckt. (Pinout) NumberLN02800259 Description8 x 8 Analog Array;includes 6-64 decoder

Contextual Info: MT8808AC Linear ICs Crosspoint Switch Circuit status Military/High-RelN Nom. Supp V 10 Minimum Operating Temp (øC)-40 Maximum Operating Temp (øC)85 Package StyleDIP Mounting StyleT Pinout Equivalence Code28-259 # Pins28 Ckt. (Pinout) NumberLN02800259 Description8 x 8 Analog Array;includes 6-64 decoder

Contextual Info: MT8808AP Linear ICs Crosspoint Switch Circuit status Military/High-RelN Nom. Supp V 10 Minimum Operating Temp (øC)-40 Maximum Operating Temp (øC)85 Package StyleQCC-J Mounting StyleS Pinout Equivalence Code28-259 # Pins28 Ckt. (Pinout) NumberLN02800259

74hc259n

Abstract: 74HC259M
Contextual Info: „ r Revised February 1999 SEMICONDUCTOR TM MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The M M 74H C 259 device utilizes advanced silicon-gate C M OS technology to im plem ent an 8-bit addressable latch, designed fo r general purpose storage a pplications in digital

Contextual Info: 259 54F/74F259 Connection Diagrams 8-Bit Addressable Latch Mil Tire T2|pii|i|p^h-speed 8-bit addressable latch designed for general purposedMV^vCwlM^ations in digital systems. It is a multifunctional device camkbfc^ajprinajBinale line data in eight addressable latches,

LS259

Abstract: als259 AIS259 11j05
Contextual Info: 259 AVG Semiconductors DDT Technical Data DV74LS259 DV74ALS259 8-Bit Addressable Latch This dovico is dosigned lor gonoral purpose storage applications m digital systems. It is a multifunctional device capable of storing single lino data in eight addressable latches, and also

Contextual Info: S eptem ber 1983 Revised February 1999 EMICONDUCTGRTM MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description The M M 74H C 259 device utilizes advanced silicon-gate CM O S technology to im plem ent an 8-bit addressable latch, designed for general purpose storage a pplications in digital

RP168

Abstract: EB7005 tektronix gigabert 1400 generator asi paralell RP178-1996
Contextual Info: PRO-LINX GS7005 Complete Serial Digital Video Receiver PRELIMINARY DATA SHEET DESCRIPTION • SMPTE 259-C compliant The GS7005 is a BiCMOS integrated circuit capable of operating as a complete 270Mb/s Serial Digital Video receiver. The GS7005 provides a complete serial digital

74HC

Abstract: M16A M16D MM74HC259 MM74HC259M MM74HC259MTC MM74HC259SJ MTC16
Contextual Info: S eptem ber 1983 Revised February 1999 E M IC O N D U C T G R T M MM74HC259 8-Bit Addressable Latch/3-to-8 Line Decoder General Description T he M M 74H C 259 device utilizes advanced silicon-gate C M O S technology to im plem ent an 8-bit addressable latch,

74LS259

Abstract: 0iah
Contextual Info: <g MOTOROLA SN54/74LS259 8-BIT ADDRESSABLE LATCH The SN 54/74LS 259 is a high-speed 8-Bit Addressable Latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and

HM514405C

Abstract: HM514405CS-6 HM514405CS-7 HM514405CS-8 HM514405CTT-6 HM514405CTT-7 HM514405CTT-8 Hitachi DSA0015
Contextual Info: ADE-203-259 A Z HM514405C Series 1,048,576-word x 4-bit Dynamic Random Access Memory Rev. 1.0 Jun. 19, 1994 The Hitachi HM514405C is a CMOS dynamic RAM organized 1,048,576-word × 4-bit. HM514405C has realized higher density, higher performance and various functions by employing

Contextual Info: g M C 74A C 259 M C 74A C T259 MOTOROLA 8-Bit Addressable Latch 8-BIT ADDRESSABLE LATCH The MC74AC259/74ACT259 is a high-speed 8-bit addressable latch designed for general purpose storage applications in digital systems. It is a multifunctional device capable of storing single line data in eight addressable latches, and also a

Contextual Info: LOGIC SYMBOL 5 4 /7 4 2 5 9 — See 9334 54LS /74LS 259 Prelim inary data DESCRIPTION FEATURES The “259" is an 8-Bit Addressable Latch with these control inputs; three Address in­ puts (Aq, A i , A2 ), an active LOW Enable input (E) and an active LOW Clear input

74ALS25

Abstract: 74ALS259
Contextual Info: TYP ES SN54ALS259, SN 74ALS25 9 8-BIT A D D R ES S A B LE LATC HES D 2661, DECEMBER 1982 • S N 54A LS 259 . . . J PACKAGE 8-Bit Parallel-Out Storage Register Performs Seriaf-toParallel Conversion w ith Storage S N 74A LS259 . . . N PACKAGE {TOP VIEW •

Contextual Info: 74H C /H C T 259 MSI 8-BIT ADDRESSABLE LATCH FEA TU R ES • TYPICAL • Combines demultiplexer and 8-bit latch Serial-to-parallel capability Output from each storage bit available Random {addressable data entry Easily expandable Common reset input Useful as a 3-to-8 active H IG H

Contextual Info: PRELIMINARY CMOS WINDOW RAM KM4232W259 D E S C R IP T IO N F E A T U R E S • 1MByte Frame-Buffer on a single chip The KM4232W 259 is a 1MByte Dual Ported DRAM • 1.6 G-Bytes/Second Internal Bus: with added features that accelerate graphic operations in a

74hc259e

Abstract: LS259 hc259
Contextual Info: MOTOROLA SEM IC O N D U C TO R TECHNICAL DATA MC54/74HC2 59 8-Bit A ddressable Latch 1-of-8 Decoder High-Perform ance Silicon-G ate C M O S The M C 54/74H C 259 is identical ¡n pinout to the LS259. The device inputs are compatible with standard C M O S outputs; with pullup resistors, they are compatible