2567 CP Search Results

Contextual Info: IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND COMMERCIAL TEMPERATURE RANGES IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS Integrated Device Technology, Inc.

2567 cp

Abstract: phl 825
Contextual Info: IDT54/74FCT821AT/BT/CT, 823/825AT/BT/CT/DT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS MILITARY AND INDUSTRIAL TEMPERATURE RANGES IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS Integrated Device Technology, Inc.

T2825

Abstract: tw 2823
Contextual Info: ¡¡srs^ HIGH-PERFORMANCE IDT54/74FCT821/2821 AT/BT/CT/DT CMOS BUS IDT54/74FCT823/2823AT/BT/CT/DT INTERFACE REGISTERS 'DT54/74FCT825/2825AT/BT/CT dt) •o 1 1 ice Technology« Inc. FEATURES: bus interface registers are designed to eliminate the extra packages required to buffer existing registers and provide

Contextual Info: HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • Common features: The FCT82xT series Is built using an advanced dual metal CM OS technology. The FCT82xT series bus interface regis­

S0242

Contextual Info: HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT Hhtegiated D ev ize T ech n ology, l i e . FEATURES: DESCRIPTION: • Common features: The FCT82xT series is built using an advanced dual metal

H2567

Contextual Info: HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT îite g z a te d D ev ice T ech n ology, l i e . FEATURES: DESCRIPTION: • Common features: The FCT82xT series is built using an advanced dual metal

D0232

Contextual Info: HIGH-PERFORMANCE CMOS BUS INTERFACE REGISTERS IDT54/74FCT821AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825AT/BT/CT In te g ra te d D e v ic e T e c h n o lo g y , Inc. FEATURES: DESCRIPTION: • Common features: The FCT82xT series is built using an advanced dual metal

Contextual Info: PRELIMINARY COM’L: -7/10/12/15 IND: -10/12/15/20 The MACH5-512/MACH5LV-512 AMD£I M A C H 5 -5 1 2 /1 2 0 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /1 6 0 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /1 8 4 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /1 9 2 -7 /1 0 /1 2 /1 5 /2 0 M A C H 5 -5 1 2 /

311P822MC

Abstract: 4998B K2A110FFDTABH 311P822 mpc 1237 Hypertronics GSFC S-311 K2A110FMDTBH T2066
Contextual Info: cPCI Series 2mm cPCI Series (2mm) Connectors Interchangeable with cPCI COTS Systems • Hypertac contacts provide the highest reliability available • Standard 2mm footprint of cPCI PICMG 2.0 • Immune to shock and vibration • High-temperature LCP insulator meets NASA

mpc 1237

Abstract: ZK2000-001-01 311P822MC 311P822 ZK2000-001-03 S50476 ZK2000-002-01 t2082 ZK2000-001-05 ZK2000-002-05
Contextual Info: cPCI Series 2mm cPCI Series (2mm) Connectors Interchangeable with cPCI COTS Systems • • • • • • Hi-Rel and Space Grade Versions Standard 2mm Footprint of cPCI PICMG 2.0 Immune to Shock and Vibration LCP Insulator meets NASA Outgassing Requirements

TFK U 111 B

Abstract: D3S94 74ACT11802
Contextual Info: 74ACT11802 TRIPLE 4-INPUT OR/NOR GATE S CAS153A - D3594, JULY 1990 - REVISED APRIL 1993 Inputs Are TTL-Voltage Compatible DW OR NT PACKAGE TOP VIEW Flow-Through Architecture Optimizes PCB Layout 1 2 3 4 5 6 7 8 9 10 3 Z [ 11 3 D [ 12 1a [ 1y [ 1Z [ 2Y[ gnd[

Contextual Info: 74ACT11802 TRIPLE 4-INPUT OR/NOR GATE SCAS153A- D3594, JULY 1990-R EV ISE D APRIL1993 DW OR NT PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin Vc c and GND Configurations Minimize High-Speed Switching Noise

Contextual Info: HIGH-PERFORMANCE CMOS BUS I NTERFACE R E GI S T E RS IDT54/74FCT821 AT/BT/CT IDT54/74FCT823AT/BT/CT/DT IDT54/74FCT825 AT/BT/CT FEATURES: DESCRIPTION: • C o m m o n features: The FC T82xT series is built using an advanced dual metal CM O S technology. The FC T82xT series bus interface regis­

Contextual Info: HARRIS SEHICOND SECTOR blE D »< HARRIS W • 4305271 004b733 Sb7 ■ H A S SEMICONDUCTOR H A -5177 B I * M M Ultra-Low O ffset Voltage Operational Amplifier March1893 Features Description • Low Offset Voltage. . . . . • Low Offset Voltage D rift

MACH355

Abstract: 29MA16 mach 1 family amd MACH436 vantis PAL 22V10 MACH111-15 PALCE610
Contextual Info: Product HIGHLIGHTS • MACH 1–5 CPLD Families ■ Fastest speeds; Easiest-to-Use ■ SpeedLocking Fixed, Guaranteed Timing ■ 32–512 Macrocells; 32–256 I/Os ■ JTAG-ISP; 3.3-V or 5-V Solutions ■ PCI-Compliance at 5, 7, 10 and 12ns ■ EECMOS Technology Leadership

vantis PAL 22V10

Abstract: 29MA16 mach111-15 Vantis macro gates
Contextual Info: Product Menu HIGHLIGHTS • MACH 1–5 CPLD Families ■ Fastest speeds; Easiest-to-Use ■ SpeedLocking Fixed, Guaranteed Timing ■ 32–512 Macrocells; 32–256 I/Os ■ JTAG-ISP; 3.3-V or 5-V Solutions ■ PCI-Compliance at 5, 7, 10 and 12ns ■ EECMOS Technology Leadership

Contextual Info: VAN T I S BE Y O N D PERFORMANCI-, Product Menu An AMD .om pan \ HIGHLIGHTS MACH 1 -5 CPLD Families Fastest speeds; Easiest-to-Use SpeedLocking (Fixed, Guaranteed Timing 3 2-51 2 Macrocells; 32-256 l/Os JTAG-ISP; 3 .3 -V or 5 -V Solutions PCI-Compliance at 5, 7, 10 and 12ns

Contextual Info: 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS TI0097— 0 2 9 5 7 , JULY 1987— REVISED MARCH 1990 54AC11646 . . . JT PACKAGE 74AC11646 . . . DW OR NW PACKAGE • Independent Registers for A and B Buses • Multiplexed Real-Time and Stored Data

20V8

Abstract: PALCE20V8 20L8
Contextual Info: PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL Device • QSOP package available — 10, 15, and 25 ns com’l version Features • Active pull-up on data input pins • Low power version 20V8L — 55 mA max. commercial (15, 25 ns) — 15, and 25 ns military/industrial versions

5D-13

Abstract: 6a7 Marking cadence leapfrog O223 6b14
Contextual Info: M ACH 5 FAMI LY X FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-512/MACH5LV-512 MACH5-512/120-7/10/12/15 MACH5-512/192-7/10/12/15 MACH5LV-512/160-7/10/12/15 MACH5LV-512/256-7/10/12/15 MACH5-512/160-7/10/12/15 MACH5-512/256-7/10/12/15 MACH5LV-512/184-7/10/12/15

5D-13

Abstract: 5D14 chip Marking 3A0 7B12
Contextual Info: MACH 5 FAMILY X FINAL COM’L:-7/10/12/15 IND:-10/12/15/20 MACH5-512/MACH5LV-512 MACH5-512/120-7/10/12/15 MACH5-512/192-7/10/12/15 MACH5LV-512/160-7/10/12/15 MACH5LV-512/256-7/10/12/15 MACH5-512/160-7/10/12/15 MACH5-512/256-7/10/12/15 MACH5LV-512/184-7/10/12/15

20V8

Abstract: 20L8 PALCE20V8
Contextual Info: 20V8 PALCE20V8 Flash Erasable, Reprogrammable CMOS PAL Device Features • QSOP package available — 10, 15, and 25 ns com’l version • Active pull-up on data input pins • Low power version 20V8L — 55 mA max. commercial (15, 25 ns) — 15, and 25 ns military/industrial versions

Contextual Info: TEXAS INSTR LOGIC 31E D Bl 6Tbl753 QQfifl^ST 2 Bi TII3 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS o , WITH 3-STATE OUTPUTS \ • • • • — J / J " O ' C > TI0097— D2957, JU LY 1987— REVISED MARCH 1990 54AC 11646 . . . J T PACKAGE

TJ53L

Abstract: 54AC11646 74AC11646 D2957
Contextual Info: TEXAS I NSTR LOGIC 3i E » m 6^1723 aoaflisi 2 miii3 54AC11646, 74AC11646 OCTAL BUS TRANSCEIVERS AND REGISTERS WITH 3-STATE OUTPUTS \ — ' V— ) C > TI0097— D2957i JULY 1987— REVISED MARCH 1990 54AC11646 JT PACKAGE 74AC11646 . . . DW OR NW PACKAGE