256 X 118 Search Results

72V845L15

Abstract: IDT72V205 IDT72V215 IDT72V225 IDT72V235 IDT72V805 IDT72V815 IDT72V825 IDT72V835 IDT72V845
Contextual Info: IDT72V805/72V815/72V825/72V835/72V845 3.3 VOLT CMOS Dual SyncFIFO 256 x 18-BIT, 512 x 18, 1,024 x 18, 2,048 x 18 and 4,096 x 18 COMMERCIAL TEMPERATURE RANGES 3.3 VOLT CMOS DUAL SyncFIFO™ DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18

Contextual Info: IDT723623 IDT723633 IDT723643 CMOS BUS-MATCHING SyncFIFOTM 256 x 36, 512 x 36, 1,024 x 36 FEATURES: • • • • • • • • • Memory storage capacity: IDT723623 – 256 x 36 IDT723633 – 512 x 36 IDT723643 – 1,024 x 36 Clocked FIFO buffering data from Port A to Port B

Contextual Info: 24C04A & Microchip 4K 512 x 8 CMOS Serial Electrically Erasable PROM FEATURES DESCRIPTION Low power CMOS technology The Microchip Technology Inc. 24C04A is a 4K bit Organized as two blocks of 256 bytes (2 x 256 x 8) Hardware write protect for upper block

IDT72205LB

Abstract: IDT72215LB IDT72225LB IDT72235LB IDT72245LB IDT72805LB IDT72815LB IDT72825LB IDT72835LB IDT72845LB
Contextual Info: CMOS DUAL SyncFIFO DUAL 256 x 18, DUAL 512 x 18, DUAL 1,024 x 18, DUAL 2,048 x 18 and DUAL 4,096 x 18 FEATURES: • • • • • • • • • • • The IDT72805LB is equivalent to two IDT72205LB 256 x 18 FIFOs The IDT72815LB is equivalent to two IDT72215LB 512 x 18 FIFOs

S73WS256N

Abstract: din 82 RGV
Contextual Info: S73WS256N Based MCPs Stacked Multi-Chip Product MCP 512/256 Megabit (32M/16M x 16-bit) CMOS 1.8 Volt-only, Simultaneous Read/Write, Burst Mode Flash Memory with 256/128 Megabit (4M/2M x 16-bit x 4 Banks) Mobile SDRAM on Shared Data Bus ADVANCE INFORMATION

24LC16b1

Abstract: 4L16I 24LC16B Data Sheet 24LC16B 4L16 MS-001 24LC16BI 24LC16B/E/ST
Contextual Info: M 24LC16B 16K 2.5V I2C Serial EEPROM FEATURES DESCRIPTION • Single supply with operation down to 2.5V • Low power CMOS technology - 1 mA active current typical - 10 µA standby current typical at 5.5V - 5 µA standby current typical at 3.0V • Organized as 8 blocks of 256 bytes 8 x 256 x 8

Electro SEX

Abstract: ge cr21 100 1r0
Contextual Info: CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DAC ADV7151 ANALO G D E V IC E S FEATURES 220 M Hz, 10-Bit 30-Bit Gam m a Corrected Pseudo Color (Indexed-Color) Triple 10-Bit "G am m a Correcting" D /A Converters Triple 256 x 10 (256 x 30) Color Palette RAM

kiv 249

Abstract: kiv 247 diode diode KIV 63 diode KIV 62 ADV7151 ADV7151LS110 ADV7151LS135 ADV7151LS170 ADV7151LS220 ADV7151LS85
Contextual Info: CMOS 220 MHz Pseudo-Color Graphics Triple 10-Bit Video RAM-DAC A N A LO G D E V IC E S ADV7151 FEATURES 220 M Hz, 10-Bit 30-Bit Gam m a Corrected Pseudo Color (Indexed-Color) Triple 10-Bit "G am m a Correcting" D /A Converters Triple 256 x 10 (256 x 30) Color Palette RAM

72V3624

Abstract: IDT72V3624 IDT72V3634 IDT72V3644
Contextual Info: 3.3 VOLT CMOS SyncBiFIFO WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Integrated Device Technology, Inc. PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings

IDT723626

Abstract: IDT723636 IDT723646
Contextual Info: CMOS Triple Bus SyncFIFOTM With Bus-Matching 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2 FEATURES: PRELIMINARY IDT723626 IDT723636 IDT723646 ♦ ♦ Big- or Little-Endian format for word and byte bus sizes Master Reset clears data and configures FIFO, Partial Reset

IDT72V3642

Abstract: IC51-1324-828 IDT72V3622 IDT72V3632 IDT72V3632L20
Contextual Info: 3.3 VOLT CMOS SyncBiFIFOTM 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: IDT72V3622 IDT72V3632 IDT72V3642 Select IDT Standard timing using EFA, EFB, FFA and FFB flags functions or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions)

72V3624

Abstract: IDT72V3624 IDT72V3634 IDT72V3644 256 x 8 bit SRAM
Contextual Info: 3.3 VOLT CMOS SyncBiFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: PRELIMINARY IDT72V3624 IDT72V3634 IDT72V3644 • Big- or Little-Endian format for word and byte bus sizes • Master Reset clears data and configures FIFO, Partial Reset

IDT723626

Abstract: IDT723636 IDT723646
Contextual Info: CMOS Triple Bus SyncFIFO With Bus-Matching 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 Integrated Device Technology, Inc. PRELIMINARY IDT723626 IDT723636 IDT723646 NOTE: There are two errata notices at the end of this data sheet. The corrections have already been incorporated

723666

Abstract: IDT723656 IDT723666 IDT723676
Contextual Info: CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2 FEATURES: PRELIMINARY IDT723656 IDT723666 IDT723676 five default offsets 8, 16, 64, 256 and 1024 Serial or parallel programming of partial flags Big- or Little-Endian format for word and byte bus sizes

memory card circuit diagram

Contextual Info: V826632B24SA 256 MB 200-PIN DDR UNBUFFERED SODIMM 32M x 64 Features Description • JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module SODIMM ; 33,554,432 x 64 bit organization. ■ Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages

Contextual Info: V826732B24SA 256 MB 200-PIN DDR UNBUFFERED SODIMM 32M x 64 Features Description • JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module SODIMM ; 33,554,432 x 64 bit organization. ■ Utilizes High Performance 32M x 16 DDR SDRAM in TSOP-II Packages

Contextual Info: V826632B24SA 256 MB 200-PIN DDR UNBUFFERED SODIMM 32M x 64 Features Description • JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module SODIMM ; 33,554,432 x 64 bit organization. ■ Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages

Contextual Info: V826632B24SC 256 MB 200-PIN DDR UNBUFFERED SODIMM 32M x 64 Features Description • JEDEC 200 Pin DDR Unbuffered Small-Outline, Dual In-Line memory module SODIMM ; 33,554,432 x 64 bit organization. ■ Utilizes High Performance 16M x 16 DDR SDRAM in TSOPII-66 Packages

IDT72V3626

Abstract: IDT72V3636 IDT72V3646
Contextual Info: IDT72V3626 IDT72V3636 IDT72V3646 3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2 FEATURES: • Serial or parallel programming of partial flags • Big- or Little-Endian format for word and byte bus sizes • Master Reset clears data and configures FIFO, Partial Reset

168-PIN

Abstract: V436616R24V
Contextual Info: MOSEL VITELIC V436616R24V L 128 MB 168-PIN UNBUFFERED DIMM 3.3 VOLT 16M x 64 LOW PROFILE PRELIMINARY Features Description • 168 Pin Unbuffered 16, 777, 216 x 64 bit Oganization SDRAM DIMM ■ Utilizes High Performance 256 Mbit, 16M x 16 SDRAM in TSOPII-54 Packages

72V3623

Abstract: IDT72V3623 IDT72V3633 IDT72V3643
Contextual Info: 3.3 VOLT CMOS SyncFIFO WITH BUS-MATCHING 256 x 36, 512 x 36, 1,024 x 36 Integrated Device Technology, Inc. PRELIMINARY IDT72V3623 IDT72V3633 IDT72V3643 • Big- or Little-Endian format for word and byte bus sizes • Reset clears data and configures FIFO, Partial Reset

71WS512ND

Contextual Info: S71WS512Nx0/S71WS256Nx0 Based MCPs Stacked Multi-chip Product MCP 256/512 Megabit (32M/16M x 16 bit) CMOS 1.8 Volt-only Simultaneous Read/Write, Burst-mode Flash Memory with 128/64Megabit (8M/4M x 16-Bit) pSRAM ADVANCE INFORMATION Distinctive Characteristics

Contextual Info: V58C2256 804/404/164 SC HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B 5 6 7 DDR400 DDR400 DDR333 DDR266 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)

Contextual Info: V58C2256 804/404/164 SA HIGH PERFORMANCE 256 Mbit DDR SDRAM 4 BANKS X 8Mbit X 8 (804) 4 BANKS X 4Mbit X 16 (164) 4 BANKS X 16Mbit X 4 (404) 5B 5 6 7 DDR400 DDR400 DDR333 DDR266 7.5 ns 7.5 ns 7.5 ns 7.5ns Clock Cycle Time (tCK2.5) 5ns 6ns 6 ns 7ns Clock Cycle Time (tCK3)