25 MHZ TXC Search Results

Contextual Info: Si106x/108x Ultra-Low Power MCU with Integrated High-Performance Sub-1 GHz Transceiver Ultra-low power 8051 µC Core - 25 MHz, single-cycle 8051 compatible CPU - 25 MIPS peak throughput with 25 MHz clock - Industry's lowest active and sleep currents - 160 µA/MHz: active mode

Contextual Info: Si106x/108x Ultra-Low Power MCU with Integrated High-Performance Sub-1 GHz Transceiver Ultra-low power 8051 µC Core - 25 MHz, single-cycle 8051 compatible CPU - 25 MIPS peak throughput with 25 MHz clock - Industry's lowest active and sleep currents - 160 µA/MHz: active mode

T120 crystal

Contextual Info: DP83932C,DP83932C-20,DP83932C-25, DP83932C-33 DP83932C DP83932C-20 DP83932C-25 DP83932C-33 MHz SONIC TM Systems-Oriented Network Interface Controller Literature Number: SNLS074A DP83932C-20 25 33 MHz SONIC TM Systems-Oriented Network Interface Controller

T12.B National

Contextual Info: DP83936AVUL-20,DP83936AVUL-25, DP83936AVUL-33 DP83936AVUL-20/25/33 MHz Full Duplex SONIC TM -T Systems-Oriented Network Interface Controller with Twisted Pair Interface Literature Number: SNLS105A DP83936AVUL-20 25 33 MHz Full Duplex SONIC TM -T Systems-Oriented Network Interface Controller

BS-28 POWER TRANSFORMER

Abstract: ECS MOTHERBOARD pcb CIRCUIT diagram
Contextual Info: DP83934 DP83934CVUL-20/25 MHz SONIC TM -T Systems-Oriented Network Interface Controller with Twisted Pair Interface Literature Number: SNLS088A DP83934CVUL-20 25 MHz SONIC TM -T Systems-Oriented Network Interface Controller with Twisted Pair Interface General Description

mlt 22 612

Abstract: nrzi clock recovery mlt resistor MX98705 mlt 44 pin
Contextual Info: PRELIMINARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES • Five Bit TTL Nibble at 25 MHz Input/Output • 25 MHz received recovery clock • Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB • Single +5V Supply • 52 PQFP package

nrzi to nrz converter circuit diagram

Abstract: nrzi to nrz circuit diagram MX98705 Mlt-3
Contextual Info: INDEX PRELIMINARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES • Five Bit TTL Nibble at 25 MHz Input/Output • 25 MHz received recovery clock • Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB • Single +5V Supply • 52 PQFP package

sil160

Abstract: SiI160 D10L9Q52
Contextual Info: Sil 160 PanelLink Digital Transmitter February 1999 Features General Description T he S i I I 60 transm itter uses PanelLink Digital technology to support Scaleable Bandwidth: 25-162 MHz VGA to UXGA displays ranging from VG A to UXG A resolutions (25-162 MHz). The S iI I 60

Contextual Info: PRELIM INARY MX98705 100 BASE-TX PHY-PMD TRANSCEIVER 1. FEATURES Five Bit TTL Nibble at 25 MHz Input/Output 25 MHz received recovery clock Operates over 100 Meters of STP and Category 5 UTP Cable >7.5 dB Single +5V Supply 52 PQFP package • Complies with IEEE 802.3 Standards

SiT8208

Abstract: SiT9121
Contextual Info: SiT9120 Standard Frequency Differential Oscillator The Smart Timing Choice The Smart Timing Choice Features Applications  31 standard frequencies from 25 MHz to 212.5 MHz  LVPECL and LVDS output signaling types  0.6 ps RMS phase jitter random over 12 kHz to 20 MHz bandwidth

80C51

Abstract: MSU2958 MSU2958C16 MSU2958C25 MSU2958C40 ZD 103
Contextual Info: • ■ MSU2958 Preliminary MOSEL VITEUC INC. ü September 1999 8 Product List - Bit Micro-controller with 3SKB flash embedded MSU2958 C 1 6 ,16 MHz 32 KB internal memory MCU MSU2958 C25, 25 MHz 32 KB internal memory MCU MSU2958 C40,40 MHz 32 KB internal memory MCU

SiT8208

Abstract: SIT9120
Contextual Info: SiT8225 0.3 ps Jitter Oscillator for Networking The Smart Timing Choice The Smart Timing Choice Features Applications  25 MHz, 25.001200 MHz and 25.000625 MHz for Ethernet applications  SATA, SAS, Ethernet, 10Gb Ethernet, XAUI  100% pin-to-pin drop-in replacement to quartz-based oscillators

ATS 16Mhz

Abstract: 80C51 MSU2958 MSU2958C16 MSU2958C25 MSU2958C40 ZD 103 ma
Contextual Info: •■ MSU2958 Preliminary MOSEL VITEUC INC. Ü September 1999 8 - Bit Micro-controller Product List with 3P.KB Hash embedded MSU2958 C l 6 ,16 MHz 32 KB internal memory MCU MSU2958 C25, 25 MHz 32 KB internal memory MCU MSU2958 C40,40 MHz 32 KB internal memory MCU

SiT9120

Abstract: SiT9121
Contextual Info: SiT9120 Standard Frequency Differential Oscillator The Smart Timing Choice The Smart Timing Choice™ Features Applications „ 31 standard frequencies from 25 MHz to 212.5 MHz „ 10GB Ethernet, SONET, Synchronous Ethernet, SATA, SAS, Fibre Channel, PCI-Express

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: TFP510 TI PanelBusā DIGITAL TRANSMITTER SLDS146B – JANUARY 2002 – REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

DST7066

Contextual Info: Token Ring Integrated Filter Module Features Includes both Transmit and Receive channels in one module Complies with IEEE 802.5 Current Proposal for UTP Cable Electrical Specifications @ 25°C EPT7066 PCA Part Number s 24 MHz Insertion Loss 1-16 MHz Transmit

TFP510

Abstract: SiI164 SiI168
Contextual Info: TFP510 TI PanelBusā DIGITAL TRANSMITTER SLDS146B – JANUARY 2002 – REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

SiI164

Abstract: SiI168 TFP510
Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

SiI164

Abstract: SiI168 TFP510 mda Signal Generator
Contextual Info: TFP510 TI PanelBusā DIGITAL TRANSMITTER SLDS146B – JANUARY 2002 – REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface

SiI164

Abstract: SiI168 TFP510
Contextual Info: TFP510 TI PanelBusā  DIGITAL TRANSMITTER SLDS146B − JANUARY 2002 − REVISED DECEMBER 2002 D Digital Visual Interface DVI Compliant1 D Supports Resolutions From VGA to UXGA D D (25-MHz–165-MHz Pixel Rates) D Universal Graphics Controller Interface