24 T0 5 Search Results

atmel 80C52X2

Abstract: 80C52X2 AT89C5131A-RD at89c5131 parallel programmer AT89C5131 PLCC 52 AT89C5131 80C51 80C52 AT89C5131A-L PLCC52
Contextual Info: Features • 80C52X2 Core 6 Clocks per Instruction • • • • • • • • • • • • • • • • • • • – Maximum Core Frequency 48 MHz in X1 Mode, 24 MHz in X2 Mode – Dual Data Pointer – Full-duplex Enhanced UART (EUART) – Three 16-bit Timer/Counters: T0, T1 and T2

16Mb SDRAM

Abstract: MT48LC1M16A1 16MSDRAM
Contextual Info: 16Mb: x16 IT SDRAM SYNCHRONOUS DRAM MT48LC1M16A1 SIT - 512K x 16 x 2 banks INDUSTRIAL TEMPERATURE For the latest data sheet, please refer to the Micron Web site: www.micronsemi.com/datasheets/sdramds.html FEATURES PIN ASSIGNMENT Top View 50-Pin TSOP • PC100 functionality

SI Prog

Abstract: PIC16Fxx SDE2506 Tiny12 AT90Sxx SOCKET-DIP40 SPI 25xxx PCF85XX nvm3060 SOCKET-DIP28S
Contextual Info: 1 2 3 4 5 6 7 8 R2 AT90S1200/2313 R9 10K BC557 U6 R15 Select power ext/int R11 4K7 JP2 JUMP3 R8 10K BC547 NB External power is needed only with some consuming device like non C-MOS devices see documentation for more info . Don't replace LM2936-Z5 with other regulators like LM78L05

ic 812

Abstract: USB3250-ABZJ 56-PIN CRC-16 GT3200 GT3200-JD GT3200-JN USB3250
Contextual Info: GT3200 64-PIN TQFP PACKAGES USB3250 (56-PIN QFN PACKAGE) USB2.0 PHY IC PRODUCT FEATURES • ■ ■ ■ ■ ■ ■ ■ Datasheet USB-IF "Hi-Speed" certified to USB2.0 electrical specification Interface compliant with the UTMI specification (60MHz 8-bit unidirectional interface or 30MHz 16-bit

dax6

Abstract: Mobile SDRAM
Contextual Info: V55C1256164MG 256Mbit MOBILE SDRAM 1.8 VOLT, TSOP II / FBGA PACKAGE 16M X 16 75 9 10 System Frequency fCK 133 MHz 111 MHz 100MHz Clock Cycle Time (tCK3) 7.5ns 9.0 ns 10 ns Clock Access Time (tAC3) CAS Latency = 3 6.0 ns 7.0 ns 8.0ns • Available in 54-ball FBGA (with 9x6 ball array

W632GG6KB

Abstract: W632GG6KB15I
Contextual Info: W632GG6KB 16M  8 BANKS  16 BIT DDR3 SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

W631GG6KB-12

Abstract: W631GG6KB-15 W631GG6KB15A DDR3 DIMM SPD JEDEC 24si 9x13 W631GG6KB15K w631gg6k W631GG6KB12I W631GG6KB-15I
Contextual Info: W631GG6KB 8M  8 BANKS  16 BIT DDR3 SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

MT48LC2M32B2P

Abstract: MT48LC2M32B2 MT48LC2M32B2P-7 MT48LC2M32B2TG 2M32B2 *48LC2M32 H9612
Contextual Info: 64Mb: x32 SDRAM Features Synchronous DRAM MT48LC2M32B2 – 512K x 32 x 4 banks For the latest data sheet, refer to Micron’s Web site Features Table 1: • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock

09005aef811ce1d5

Abstract: MT48LC2M32B2 MT48LC2M32B2TG-7G
Contextual Info: 64Mb: x32 SDRAM SYNCHRONOUS DRAM MT48LC2M32B2 - 512K x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds FEATURES • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock

MT48LC2M32B2

Contextual Info: 64Mb: x32 SDRAM SYNCHRONOUS DRAM MT48LC2M32B2 - 512K x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds FEATURES • PC100 functionality • Fully synchronous; all signals registered on positive edge of system clock

Contextual Info: V54C365 16/80/40 4VE 64Mbit SDRAM 3.3 VOLT, TSOP II / FBGA 4M X 16, 8M X 8, 16M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns

V54C3128

Contextual Info: V54C3128 16/80/40 4VB 128Mbit SDRAM 3.3 VOLT, TSOP II / FBGA 8M X 16, 16M X 8, 32M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns

mt48lc32m16a2p-75

Abstract: MT48LC32M16A2P-75C 1m x16 SDRAM MICRON A11 MARKING CODE MT48LC32M16A2P MT48LC128M4A2 MT48LC32M16A2 MT48LC64M8A2 TN-48-05 MT48LC32M16A2P-75 c
Contextual Info: 512Mb: x4, x8, x16 SDRAM Features Synchronous DRAM MT48LC128M4A2 – 32 Meg x 4 x 4 banks MT48LC64M8A2 – 16 Meg x 8 x 4 banks MT48LC32M16A2 – 8 Meg x 16 x 4 banks For the latest data sheet, refer to Micron’s Web site Features Options • PC100- and PC133-compliant

Contextual Info: ADVANCE‡ 64Mb: x16 MOBILE SDRAM SYNCHRONOUS DRAM MT48H4M16LF - 1 MEG x 16 x 4 BANKS Features Figure 1: 54-Ball FBGA Pin Assignment Top View • Temperature compensated self refresh (TCSR) • Fully synchronous; all signals registered on positive edge of system clock

Contextual Info: UNCONTROLLED DOCUMENT P IN 24 PIN 13 510 REV, 4,50 [0,1771 [0.201] A 11,00 [0 ,4 3 3 ] £ + J + + o + + + o + + REV. LDC-M2502RI A NUMBER AND REVISION COMMENTS 5 .3 .0 7 MIN PARAMETER + 565 2,2 FORWARD VOLTAGE PIN 12 EMITTED COLOR: GREEN FACE COLOR: GRAY SEGMENT COLOR:

Contextual Info: W632GU6KB 16M  8 BANKS  16 BIT DDR3L SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

Contextual Info: W631GU6KB 8M  8 BANKS  16 BIT DDR3L SDRAM Table of Contents1. GENERAL DESCRIPTION . 5 2. FEATURES . 5

Contextual Info: V54C365 16/80/40 4VE 64Mbit SDRAM 3.3 VOLT, TSOP II / FBGA 4M X 16, 8M X 8, 16M X 4 6 7PC 7 8PC System Frequency (fCK) 166 MHz 143 MHz 143 MHz 125 MHz Clock Cycle Time (tCK3) 6 ns 7 ns 7 ns 8 ns Clock Access Time (tAC3) CAS Latency = 3 5.4 ns 5.4 ns 5.4 ns

HYB18H512322BF

Abstract: qimonda hyb18h5
Contextual Info: March 2008 IDRD51-0-A1F1C–32C XDR DRAM 512-Mbit XDR DRAM RoHS compliant Data Sheet Rev. 1.0 Data Sheet IDRD51-0-A1F1C 512-Mbit XDR DRAM IDRD51-0-A1F1C–32C Revision History: 2008-03, Rev. 1.0 Page Subjects major changes since last revision All New Data Sheet

Q24S15050-NS00

Abstract: TR-332
Contextual Info: Q24S15050 Data Sheet 18-36 Vdc Input, 15 A, 5 Vdc Output The Q24S15050 surface mounted DC/DC converter offers unprecedented performance in the industry-standard quarter brick format. This is accomplished through the use of patent pending circuit and packaging techniques to achieve ultrahigh efficiency, excellent thermal performance and a very

AD847

Contextual Info: i. i « * High Speed, Low Power Monolithic Op Amp A N A LO G ► D E V IC E S CONNECTION DIAGRAM FEATURES Superior Performance High Unity Gain BW: 50 MHz Low Supply Current: 5.3 mA High Slew Rate: 300 V / a s Excellent Video Specifications 0.04% Differential Gain (NTSC and PAL

EM63A165TS-5G

Abstract: EM63A165TS-6G EM63A165TS-7G EM63A165TS cke 2009 EM63A165
Contextual Info: EtronTech EM63A165TS 16M x 16 bit Synchronous DRAM SDRAM Etron Confidential Features • • • • • • • • • • • • Fast access time from clock: 4.5/5.4/5.4 ns Fast clock rate: 200/166/143 MHz Fully synchronous operation Internal pipelined architecture

dba1

Abstract: VG3617161ET
Contextual Info: VG3617161ET 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM VIS Description The VG3617161ET is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V

dba1

Abstract: VG3617161DT
Contextual Info: VIS VG3617161DT 1,048,576 x 16 - Bit CMOS Synchronous Dynamic RAM Description The VG3617161DT is CMOS Synchronous Dynamic RAM organized as 524,288-word X 16-bit X 2-bank. It is fabricated with an advanced submicron CMOS technology and designed to operate from a single 3.3V