20APR2000 Search Results

P-51

Contextual Info: 1 5 P- Peripheral 8051 System on a Chip P-51 Features All 8051/52 resources: EISA/PC-104 interface: ! ! ! ! ! ! ! ! VDD P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1 P1.0 BCLK RFRSH GND GND GND IRQ15 IRQ14 IRQ12 IRQ11 IRQ10 IRQ9 IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 45 EISA signals supported.

SOH28

Abstract: M48Z35AV
Contextual Info: M48Z35AV 5.0V or 3.3V, 256Kbit 32Kbit x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Battery low flag (BOK) ■ Automatic power-fail chip deselect and WRITE

STANDARD DIN 6784

Contextual Info: M48Z35AV 5.0 V or 3.3 V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Battery low flag (BOK) ■

COP*ACC7

Contextual Info: COP8ACC5 8-Bit CMOS ROM Based Microcontrollers with 4k Memory and High Resolution A/D General Description The COP8ACC5 ROM based microcontrollers are highly integrated COP8 Feature core devices with 4k memory and advanced features including a High-Resolution A/D. These

M48Z35AV

Abstract: SOH28
Contextual Info: M48Z35AV 5.0 V or 3.3 V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Battery low flag (BOK) ■ Automatic power-fail chip deselect and WRITE

VUINT16

Abstract: TPU MASK AN1778 MPC500 MPC555 TPUPN03
Contextual Info: Freescale Semiconductor, Inc. Application Note AN2363/D Rev. 0, 10/2002 Freescale Semiconductor, Inc. Using the Frequency Measurement TPU Function FQM with the MPC500 Family Randy Dees TECD Applications This TPU Programming Note is intended to provide simple C interface routines to the

DIN 6784

Abstract: M48Z35AV SOH28
Contextual Info: M48Z35AV 5.0 V or 3.3 V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Battery low flag (BOK) ■

Contextual Info: M48Z35AV 5.0 V or 3.3 V, 256 Kbit 32 Kbit x 8 ZEROPOWER SRAM Not recommended for new design Features • Integrated, ultra low power SRAM, power-fail control circuit, and battery ■ READ cycle time equals WRITE cycle time ■ Battery low flag (BOK) ■

vuint16

Abstract: singlestep AN1778 MPC500 MPC555 TPUPN03 VUINT32 0x306002
Contextual Info: Freescale Semiconductor Application Note AN2363/D Rev. 0, 10/2002 Freescale Semiconductor, Inc. Using the Frequency Measurement TPU Function FQM with the MPC500 Family Randy Dees TECD Applications This TPU Programming Note is intended to provide simple C interface routines to the

Contextual Info: 7 8 THIS DRAWING IS UNPUBLISHED. C COPYRIGHT RELEASED FOR PUBLICATION 6 5 4 2 19 LOC ALL RIGHTS RESERVED. 19 SECTION PART NUMBER #284478-1 FOR REF. AS SHOWN SECTION 3 A-A I 6 B-B X =5x N.POS-1 26.9 1 REVISIONS DIST - P LTR 5 REF. REF. 0.3 A DATE DWN APVD