2 IN PUT TTL XOR GATES Search Results

af201

Abstract: F2018 AM211 am 332 F2017 SEM 2005 16 PINS inverter
Contextual Info: Am3550 Mixeçt ÉCL/TTL I/O Mask-Programmable Gate Array PRELIMINARY DISTINCTIVE CHARACTERISTICS Up to 5228 equivalent gates - 576 internal cells - Up to 124 l/O s H igh-perform ance, low -pow er ECL internal gates - W orst case Tpd = 0.6 ns Hi-Speed = 0.7 ns (Medium)

Contextual Info: Lattice' ispLSr and pLSI' 2032 ; ; ; Semiconductor •■■Corporation High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers

af201

Abstract: AOX2051 Am319 AF211 AF212 AF203 AF216 AM2024 ls 11s AM211
Contextual Info: y i Am3550 MixeqT ECL/TTL I/O Mask-Programmable Gate Array • — PRELIMINARY DISTINCTIVE CHARACTERISTICS Up to 5228 equivalent gates - 576 internal cells - Up to 124 l/O s H igh-perform ance, low -pow er ECL internal gates - W orst case Tpd = 0.6 ns Hi-Speed

TR20X3

Abstract: DFI01 OR02D
Contextual Info: December 1989 FGA S eries A S PE C T- ECL G ate A rrays General Description The FGA Series is a new generation of ECL gate arrays based on National’s ASPECT process. These advanced ECL gate arrays, ranging from 200 to over 30,000 equiva­ lent gates, offer typical internal propagation delays of

ispls11024

Contextual Info: Lattice ispLSI 1024 ; ; ; Semiconductor • ■ ■ Corporation High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs

Contextual Info: Latticc ispLSI 3256 ; ; ; Semiconductor •■■ Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 1281/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Lattice ispLSr 1016 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs

Contextual Info: Q V Lattica V Ï Î i f c ispLSI3256A !Semiconductor I Corporation High Density Programmable Logic F u n c tio n a l B lo c k D iagram F eatures • HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect

SA8F

Contextual Info: 0 ^ u Lattice’ ispLSr 3256 !Semiconductor •Corporation High Density Programmable Logic F eatures F u n c tio n a l B lo c k D iagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect

Contextual Info: f C-S u Lattice ispLSI3448 !Semiconductor •Corporation Features High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 224 I/O — 20000 PLD Gates — 672 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Lattica ispLSI 3256 ;Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 128 1/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — W ide Input Gating for Fast Counters, State

Contextual Info: Lattice ispLSI and pLSF 2032 I Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 1000 PLD Gates 32 I/O Pins, Two Dedicated Inputs 32 Registers High Speed Global Interconnect

B272

Abstract: 149-IO
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

B272

Abstract: z 0607
Contextual Info: ispLSI 3192 Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic

B272

Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

Contextual Info: Lattice' ispLSI 3256A | Semiconductor I Corporation In-System Programmable High Density PLD Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 1281/0 Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

3192-70LQI

Abstract: B272
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

Contextual Info: Lattice is p L S _ _ _ _ Semiconductor • ■ ■ ■ Corporation r a n d p L S Im 1 0 1 6 E High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — — — — — 2000 PLD Gates 32 I/O Pins, Four Dedicated Inputs

Contextual Info: Lattica ispLSI 3192 ;Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

lattice 1016-60LJ

Abstract: ispls11016 ispLSI1016 til 701 1016-60 Lattice 1016-80LJ 1016-80LJ loadable counter with timing diagram
Contextual Info: Latticc ispLSI 1016 ; ; ; Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs

cd-rom circuit diagram

Abstract: PT 10000
Contextual Info: Lattice' ispLSI 3192 | Semiconductor I Corporation High Density Programmable Logic Functional Block Diagram Features HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: L a tt Ì C e * i Coipo?at?ont0r ispLSr 2096E In-System Programmable SuperFAST High Density PLD Features Functional Block Diagram SUPERFA ST HIGH DENSITY IN-SYSTEM PRO GRAM MABLE LOGIC — — — — — 4000 PLD Gates 96 I/O Pins, Two Dedicated Inputs

Contextual Info: Lattice ispLSr 1024 H I Semiconductor •■■ Corporation In-System Programmable High Density PLD Functional Block Diagram Features • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 4000 PLD Gates — 48 I/O Pins, Six Dedicated Inputs