192-B LS Search Results

T1M03

Abstract: P89C52X2 80C51 DIP40 LQFP44 P87C52 P87C52X2 P89C52 P89V52X2 P89V52X2FN
Contextual Info: P89V52X2 8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM Rev. 01 — 7 June 2007 Preliminary data sheet 1. General description The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and 192 B of data EEPROM. This device is designed to be a drop in and software compatible

80C51

Abstract: DIP40 LQFP44 P87C52 P87C52X2 P89C52 P89C52X2 P89V52X2 P89V52X2FN PLCC44
Contextual Info: P89V52X2 8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM Rev. 02 — 22 May 2008 Product data sheet 1. General description The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and 192 B of data EEPROM. This device is designed to be a drop in and software compatible

Contextual Info: P89V52X2 8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM Rev. 01 — 3 April 2008 Product data sheet 1. General description The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and 192 B of data EEPROM. This device is designed to be a drop in and software compatible

P89C52X2

Abstract: 80C51 DIP40 LQFP44 P87C52 P87C52X2 P89C52 P89V52X2 P89V52X2FN PLCC44
Contextual Info: P89V52X2 8-bit 80C51 low power 8 kB flash microcontroller with 256 B RAM, 192 B data EEPROM Rev. 03 — 4 May 2009 Product data sheet 1. General description The P89V52X2 is an 80C51 microcontroller with 8 kB flash, 256 B of data RAM, and 192 B of data EEPROM. This device is designed to be a drop in and software compatible

TAG 2,5 200

Abstract: 1AAA CY37192 CY37192V
Contextual Info: CY37192 UltraLogic 192-Macrocell ISR™ CPLD • P ro d uct-term clocking Features • IEEE 1149.1 JTAG b o u n d a ry scan • 192 m a cro c ells in tw e lv e logic blocks • P ro g ram m a b le slew rate co n tro l on ind ividu al l/O s • In-S ystem R ep ro g ra m m ab le ™ IS R ™ including:

HDR3

Abstract: AD1853
Contextual Info: AN ALO G D E V IC E S Stereo, 24-Bit, 192kHz, Multibit S A DAC AD1853* FEATURES 5 V Stereo Audio DAC System Accepts 1 6 -/1 8 -/2 0 -/2 4 -B it Data Supports 24 Bits and 192 kHz Sam ple Rate Accepts a W ide Range of Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz

Contextual Info: AN ALO G D E V IC E S Stereo, 24-Bit, 192kHz, Multibit S A DAC AD1853* FEATURES 5 V Stereo Audio DAC System Accepts 1 6 -/1 8 -/2 0 -/2 4 -B it Data Supports 24 Bits and 192 kHz Sam ple Rate Accepts a W ide Range of Sample Rates Including: 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz and 192 kHz

CY7C341

Abstract: CY7C341B 7400series ttl
Contextual Info: CY7C341B y CYPRESS Features 192-Macrocell MAX EPLD Typical lcc vs. f MAx • 192 m a cro c ells in 12 LABs • 8 d ed ic ate d inp u ts, 64 b id irec tio n al I/O pin • A d van ced 0.6 5-m icro n C M O S te c h n o lo g y to increase p erfo rm an ce • P ro g ram m a b le in te rco n n e ct array

HY6254A-I

Abstract: BDZ11 HYB254A-I
Contextual Info: H Y 5254 A-I S e rie s •H YUN D AI 8 K N B - b it CM OS SRAM DESCRIPTION The HYB254A-I is a high-spBed, low power and B,192 x B-bits CMOS sialic RAM Fabricated using Hyundai's high performance twin lub CMOS process technology. This high reliability process coupled with innovative circuit

2364 rom

Abstract: 2364-X 5L2764 ROM 2364
Contextual Info: MITSUBISHI LSIs M 5M 2364-XXXP 6 5 5 3 6 -B I T 8 192-W ORD B Y 8 -B IT M A SK -PR O G R A M M A B LE ROM DESCRIPTION PIN CONFIGURATION (TOP VIEW) The M itsubishi M 5 M 2 3 6 4 -X X X P is a 6 5 5 3 6 -b it maskprogrammable high speed read-only memory. NC

TM610

Abstract: MN103004J sbti TM210 MN1030F04K
Contextual Info: _i MN103004J / 04K / F04K 1 Type 1 Command ROM x64-Bit 1 Data RAM ( 32-Bit) 1 Minimum Instruction Execution Time 1 Interrupts MN103004J / 04K / F04K 192 K B / 128 K B / 256 KB (Flash) 4 K B / 1 0 K B /1 2 KB M N 103004J / 04K: 30 ns (at 2.2 V, 33 MHz) M N 103004J / 04K:

ltra

Contextual Info: ^ CYPRESS ADVANCED INFORMATION Ultra39192 UltraLogic 192-Macrocell CPLD Features F unctional D escription • 192 m acrocells in 12 logic blocks • In-S ystem R ep rogram m ab le ISR • Fully PCI com p liant T h e U ltra 3 9 1 9 2 is a h igh*density, hig h p e rfo rm a n c e C o m p le x P ro g ra m m a b le

IL-C-5541

Contextual Info: LENGTH 1 /4 6.4 3 / 8 (9.5) 1 /2 (12.7) 5 / 8 (15.9) 3 / 4 (19.1) 1 (25.4) FOR #4 SCREW FOR #6 SCREW FOR #8 SCREW FOR #10 SCREW A: .114 (2.9) A: .140 (3.5) A: .166 (4.2) A: .192 (4.9) B: 1 /4 (6.4) B: 1 /4 (6.4) B: 1 /4 (6.4) B: 3 / 8 (9.5) BRSS4-2 BRSS4-3

ADAPT29K

Abstract: Am29000 Users Manual
Contextual Info: Am29000 a Am29000 Advanced Micro Devices Streamlined Instruction Processor DISTINCTIVE CHARACTERISTICS B Full 32-blt, three-bus architecture • ■ 23 million Instructions per second MIPS sustained at 33 MHz ■ 192 general-purpose registers ■ 512-byte Branch Target Cache

hy 214 A Display

Abstract: MIL-R-26 apd 128*128 APD-256M026-1 APD-256M026 APD-480M021-1 irf 346
Contextual Info: A COMPANY OF. A lphabetical Index P roducts Only 7, 8, surface mount, hybrid chip th e rm istors.190 10, 20, 30, 40, 50, 60, NTC therm istors.202 300, printed circuit board connectors.293 IB , uncoated disc thermistors, material "B ". 192

0C314

Abstract: H7 RF IC-311 SP 6554 A adcb 27 TI BB cross MC68HC11D3 MC68HC711D3 S002D OC310
Contextual Info: MC68HC11D3RG/AD MC68HC11D3 MC68HC711D3 PROGRAMMING REFERENCE GUIDE M MOTOROLA 192 BYTES STATIC RAM MULTIPLEXED ADDRESS/DATA BUS • A8 A15À A D 7 - -ADO À y y y DATA DIRECTION REGISTER C DATA DIRECTION REGISTER B PO RTC PO RTB A A

tms 0119

Contextual Info: Lattice ispLSr 3192 ;Semiconductor I Corporation High Density Programmable Logic Features IH B • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

0C314

Abstract: OC310 TSX 07 2B 1628
Contextual Info: MC68HC11D3RG/AD MC68HC11D3 MC68HC711D3 PROGRAMMING REFERENCE GUIDE M MOTOROLA 192 BYTES STATIC RAM MULTIPLEXED ADDRESS/DATA BUS • A8 A15À A D 7 - -ADO À y y y DATA DIRECTION REGISTER C DATA DIRECTION REGISTER B PO RTC PO RTB A A

Contextual Info: MITSUBISHI LSIs M5M5178AP,J,FP-20,-25 65536-BIT 8 192-WORD BY 8-BIT CM0S STATIC RAM DESCRIPTION This is a fa m ily o f 8 1 9 2 w o rd b y 8 -b it s ta tic R A M s, fa b ri­ PIN CONFIGURATION (TOP VIEW) cated w ith th e high pe rform ance C M OS s illic o n gate MOS

74192 internal diagram

Abstract: 74192FC 74LS192P 74LS192DC 74LS192 INTERNAL DIAGRAM 74192 counter
Contextual Info: 1 NATIONAL SEMICOND -CLOGIO DEE D | b S D U B S _ ~ T - 9 5 DDbBiei 5 | 3 -o 9 192 CO NN ECTIO N DIAGRAM PINO UT A 54/74192 54LS /74LS192 \ UP/DOWN DECADE COUNTER I P i[T 161Vcc o.QE H ] po Qo [T With Separate U p/D ow n Clocks

Contextual Info: EPM7192 EPLD Ä N b jf e & r High-Performance 192-Macrocell Device \ Data Sheet September 1992, ver. 2 □ Features High-density, erasable CMOS EPLD based on second-generation Multiple Array MatriX MAX architecture 3,750 usable gates Combinatorial speeds with tPD = 12 ns

Contextual Info: SHARP ‘M»* fi • TO : REFERENCE DEVICE SPECIFICATION 64K MODEL bit STATIC FOR RAM B.192 X B bi t J NO. L H 5 1 6 0 N - 1 0 L ( LHÊ160N S P E C N O . ; E L 0 2 1 05 6 ISSUE: CUSTOMERS JAN 3t . 1 9 9 0 B APPROVAL DATE : PRESENTED BY: BY: Y .TORO Dept.

Contextual Info: MITSUBISHI LSIs M5M5179BP,J,FP-15,-20 7 3 7 2 8 -B IT 8 192-W ORD BY 9-B IT C M O S STATIC RAM DESCRIPTION T h is is a fa m ily o f 8 1 9 2 w o rd b y 9 -b it static R A M s , fa b r i­ PIN CONFIGURATION (TOP VIEW) cated w ith th e high p e rfo rm a n c e C M O S silicon gate M O S

ic 74192 pin diagram

Abstract: LA 4289 74192 ic 74192 counter ic 74192 74ls192 74192PC
Contextual Info: 192 C O N N E C T IO N DIAGRAM PINOUT A 54/74192 6 / * ° ^ 54LS/74LS192 O l o ü U ^ UP/DOWN DECADE COUNTER With Separate Up/Down Clocks P i[ T Tèi vcc o ,H H J po Qod 33 MR [7 T5] t c d CPd CPuU D ESCRIPTIO N — T h e ’ 192 is an u p /d o w n B C D d e c a d e (8421) co u n ter. S e p a ­