170FT Search Results

CY37064

Contextual Info: UltraLogic 64-Macrocell ISR™ CPLD — ts = 3.5 ns Features — tCo = 4 -5 ns • Product-term clocking 64 macrocells in four logic blocks In-System Reprogrammable™ ISR™ • IEEE 1149.1 JTAG boundary scan • Programmable slew rate control on individual l/Os

Contextual Info: fax id: 6140 CY7C375Ì :/ C Y P R E S S UltraLogic 128-Macrocell Flash CPLD Features • • • • Functional Description 128 macrocells in eight logic blocks 128 I/O pins 5 dedicated inputs including 4 clock pins In-System Reprogrammable ISR™ Flash technology

NCL025

Contextual Info: •■■■■■■\fct>cw.-. s a s iâ s ^ 5^” .w s & v PRELIMINARY _ . "T U ltra 3 7 5 1 2 UltraLogic 512-Macrocell ISR™ CPLD Features • • • • • 512 macrocells in 32 logic blocks • In-System Reprogrammable™ ISR™ — JTAG-compliant on-board programming

C3157

Contextual Info: fax id: 6139 CY7C374Ì :/ C Y P R E S S UltraLogic 128-Macrocell Flash CPLD Features Functional Description • 128 macrocells in eight logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins The CY7C374i is an In-System Reprogrammable Complex

Contextual Info: EL2020C F eatu res G eneral D escrip tion • • • • • • • • • The EL2020 is a fast settling, wide bandwidth amplifier opti­ mized for gains between —10 and +10. B uilt using the Elantec monolithic Complementary Bipolar process, this amplifier uses

Contextual Info: INTEGRATED CIRCUITS i m m l y i E I TI Xilinx has acquired the entire Philips CoolRunner Low Power CPLÛ Product Family, For more technical or sales information, piease see: www.xilinx.com XCR22V10 5V zero power, TotalCMOS , universal PLD device Product specification

Contextual Info: A TS42VA12 Features • • High-speed EPROM-based CMOS Multi-Function PLD Two Fully Programmable Arrays Eliminate "P-term Depletion” Up to 64 P-terms per OR Function Improved Output Macro Cell Structure Individually Programmable as: Registered Output with Feedback

Contextual Info: fax id: 6137 CY7C372Ì :/ C Y P R E S S UltraLogic 64-Macrocell Flash CPLD Fi_ASH370i™ family of high-density, high-speed CPLDs. Like all members of the FLASH370i family, the CY7C372i is de­ signed to bring the ease of use and high performance of the

CY37128P84-125JI

Contextual Info: UltraLogic 128-Macrocell ISR™ CPLD Features • 128 macrocells in eight logic blocks • In-System Reprogrammable ISR™ — JTAG-compliant on-board programming — Design changes don’t cause pinout changes — Design changes don’t cause timing changes

JIS B 7512

Abstract: el2020cn EL2020 EL2020C EL2020CM QCX0002 ML 1557 b transistor
Contextual Info: EL2020C ß liiU tB C - ,b iw w m m m c « ’Esinscir:. ;? EL2020C SO MHz Cuvirent Fficdbuck A m p lifier F e a tu re s G en era l D e sc r ip tio n • • • • • • • • • The EL2020 is a fast settling, wide bandwidth amplifier opti­ mized for gains between —10 and + 10. B uilt using the Elantec

74HCu04 oscillator application note

Abstract: 74HCU04
Contextual Info: 74HCU04 SSI J V H E X IN V E R T E R FEATURES • • Output capability: standard I q c category: SSI SYMBOL PARAMETER CONDITIONS tPHL^ t PLH propagation delay nA to nY CL = 15 pF C| input capacitance CPD power dissipation capacitance per inverter VCC = 5

JTAG

Abstract: CY37032
Contextual Info: UltraLogic 32-Macrocell ISR™ CPLD — ts = 3 ns Features — tco = 4 ns • 32 macrocells in two logic blocks • In-System Reprogrammable™ ISR™ • Product-term clocking • IEEE 1149.1 JTAG boundary scan • Programmable slew rate control on individual l/Os

Contextual Info: fax id: 6138 CY7C373Ì C'i- UltraLogic 64-Macrocell Flash CPLD • Pin compatible with the CY7C374i Features Functional Description • 64 macrocells in four logic blocks • 64 I/O pins • 5 dedicated inputs including 4 clock pins • In-System Reprogrammable ISR™ Flash technology

Contextual Info: PRELIMINARY CY37064V UltraLogic 3.3V 64-Macrocell ISR™CLPD Features — tpo = 10 ns — ts = 5.5 ns • 64 macrocells in four logic blocks • 3.3V In-System Reprogrammable™ ISR™ — tco = 6 .5 ns • • • • • • — JTAG-compliant on-board programming

SL1012

Contextual Info: fax id: 6140 CY7C375Ì C'i- UltraLogic 128-Macrocell Flash CPLD • Available in 160-pin TQFP, CQFP, and PGA packages Features Functional Description • 128 macrocells in eight logic blocks • 128 I/O pins • 5 dedicated inputs including 4 clock pins

AMAZE PLC42VA12

Abstract: 42VA12
Contextual Info: Philips Components-Signetics D ocum en t N o. 8 5 3 -1 4 1 4 EC N No. 99206 Date o f Issue March 26, 1990 S tatus Product Specification P L C 4 2 V A 12 CMOS programmable multi-function PLD Programmable Logic Devices 4 2 x 1 0 5 x 1 2 DESCRIPTION FEATURES