16JUL2008 Search Results

Contextual Info: CDCU2A877 www.ti.com SCAS827A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER • FEATURES • • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate DDR II Applications Spread Spectrum Clock Compatible

20-PIN

Abstract: DS96174 LTC487 MAX3042 MC3487 SN75174
Contextual Info: SN65LBC174A-EP QUADRUPLE RS-485 DIFFERENTIAL LINE DRIVER www.ti.com SLLS732 – OCTOBER 2006 – REVISED DECEMBER 2006 FEATURES • • • • • • • • • • • • • • 1 (2) Controlled Baseline – One Assembly/Test Site, One Fabrication

QFN16L

Abstract: ST2349A ST2349AQTR
Contextual Info: ST2349A 4-bit dual supply level translator without direction control pin Features • 18 Mbps max data rate when driven by a totem pole driver ■ 6.8 Mbps (max) data rate when driven by an open drain pole driver ■ Bi-directional level translation without

KD1084

Abstract: KD1084AD2T18R KD1084ADT-R KD1084AXX KD1084AXX18
Contextual Info: KD1084AXX KD1084AXX18 5 A low drop positive voltage regulator adjustable and fixed Features • Typical dropout 1.3 V at 5 A ■ Three terminal adjustable or fixed output voltage 1.8 V, 3.3 V. ■ Guaranteed output current up to 5 A ■ Output tolerance ±1 % at 25 °C and ± 2 % in full

ST2329AQTRQTR

Abstract: QFN10 ST2329A QFN-10
Contextual Info: ST2329A 2-bit dual supply level translator without direction control pin Features • 18 Mbps max. data rate when driven by a totem pole driver ■ 6.8 Mbps (max.) data rate when driven by an open drain pole driver ■ Bidirectional level translation without

ST2349AQTR

Abstract: JESD97 QFN16L ST2349A
Contextual Info: ST2349A 4-bit dual supply level translator without direction control pin Preliminary Data Features • 90 Mbps max data rate when driven by a totem pole driver ■ 8 Mbps (max) data rate when driven by an open drain pole driver ■ Bi-directional level translation without

Contextual Info: TLV5619ĆEP 2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN ą SGLS124A − JULY 2002 − REVISED DECEMBER 2003 D Controlled Baseline D D D D D D D D D D D D D D D applications − One Assembly/Test Site, One Fabrication Site

wk 2 94v-0

Abstract: 4130 tyco
Contextual Info: 3 THIS DRAWING IS UNPUBLISHED. RELEASED FOR PUBLICATION BY TYCO ELECTRONICS CORPORATION. COPYRIGHT L0C ALL RIGHTS RESERVED. REVISIONS DW LTR A1 P IC K PA D DATE DESCRIPTION DWN SC WK 16JUL08 REVISED ECR— 0 8 — 0 1 7 9 0 4 APVD D D - i -

Contextual Info: SN65HVD50-SN65HVD55 www.ti.com SLLS666E – SEPTEMBER 2005 – REVISED OCTOBER 2009 HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS Check for Samples :SN65HVD50-SN65HVD55 • • • • • • • • 1 1/8 Unit-Load Option Available (Up to 256 Nodes on the Bus)

TPS75101

Abstract: TPS75133Q TPS75301 TPS75315 TPS75318 TPS75325 TPS75333 TPS75333Q
Contextual Info: TPS75101ĆEP, '75115ĆEP, '75118ĆEP, '75125ĆEP, '75133ĆEP WITH POWER GOOD TPS75301ĆEP, TPS75315ĆEP, TPS75318ĆEP, TPS75325ĆEP, TPS75333ĆEP WITH RESET FASTĆTRANSIENTĆRESPONSE 1.5ĆA LOWĆDROPOUT VOLTAGE REGULATORS SGLS158 − APRIL 2003 D Controlled Baseline

SLMA002

Abstract: TPS75201M-EP TPS75201MPWPREP TSSOP-20
Contextual Info: TPS75201MĆEP FASTĆTRANSIENTĆRESPONSE 2ĆA LOWĆDROPOUT VOLTAGE REGULATOR WITH RESET SGLS325 − JANUARY 2006 D Controlled Baseline D D D D D D D D D 20-Pin TSSOP PWP PowerPAD Package − One Assembly/Test Site, One Fabrication D Thermal Shutdown Protection

Contextual Info: TLV5619ĆEP 2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN ą SGLS124A − JULY 2002 − REVISED DECEMBER 2003 D Controlled Baseline D D D D D D D D D D D D D D D applications − One Assembly/Test Site, One Fabrication Site

Contextual Info: ADS901 AD S 901 E SBAS054A – MAY 2001 10-Bit, 20MHz, +3V Supply ANALOG-TO-DIGITAL CONVERTER TM FEATURES DESCRIPTION ● LOW POWER: 48mW at +3V ● SUPPLY RANGE: +2.7V to +3.7V ● ADJUSTABLE FULL SCALE RANGE WITH EXTERNAL REFERENCES ● NO MISSING CODES

LM324N

Abstract: L324a
Contextual Info: LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066S − SEPTEMBER 1975 − REVISED JULY 2008 D D D D D D description/ordering information These devices consist of four independent

LM324N

Contextual Info: LM124, LM124A, LM224, LM224A, LM324, LM324A, LM2902, LM2902V, LM224K, LM224KA, LM324K, LM324KA, LM2902K, LM2902KV, LM2902KAV QUADRUPLE OPERATIONAL AMPLIFIERS SLOS066S − SEPTEMBER 1975 − REVISED JULY 2008 D D D D D D description/ordering information These devices consist of four independent

Contextual Info: TLV320AIC23B Stereo Audio CODEC, 8Ć to 96ĆkHz, With Integrated Headphone Amplifier Data Manual February 2004 Digital Audio Products SLWS106H IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

Contextual Info: TL16C752B-EP 3.3 V DUAL UART WITH 64-BYTE FIFO www.ti.com SGLS153B – FEBRUARY 2003 – REVISED DECEMBER 2007 FEATURES 1 • • • • • • • • • • • • • • • • 1 Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an

Contextual Info: SN54LVT8996, SN74LVT8996 3.3-V 10-BIT ADDRESSABLE SCAN PORTS MULTIDROP-ADDRESSABLE IEEE STD 1149.1 JTAG TAP TRANSCEIVERS SCBS686A – APRIL 1997 – REVISED DECEMBER 1999 D D D D D D D D D D D D D Simple Addressing (Shadow) Protocol Is Received/Acknowledged on Primary TAP

Contextual Info: 74SSTUB32865A www.ti.com SLAS562 – NOVEMBER 2007 28-BIT TO 56-BIT REGISTERED BUFFER WITH ADDRESS-PARITY TEST FEATURES 1 • Member of the Texas Instruments Widebus+ Family • Pinout Optimizes DDR2 RDIMM PCB Layout • 1-to-2 Outputs Supports Stacked DDR2

Contextual Info: TPA2005D1 www.ti.com. SLOS369F – JULY 2002 – REVISED JULY 2008 1.4-W MONO FILTER-FREE CLASS-D AUDIO POWER AMPLIFIER

in4702

Abstract: INA117 INA117AM INA117BM INA117KU INA117P INA117SM OPA27 REF200 INA117PG4
Contextual Info: INA117 INA 117 INA 117 www.ti.com High Common-Mode Voltage DIFFERENCE AMPLIFIER FEATURES APPLICATIONS ● COMMON-MODE INPUT RANGE: ±200V VS = ±15V ● PROTECTED INPUTS: ±500V Common-Mode ±500V Differential ● UNITY GAIN: 0.02% Gain Error max ● NONLINEARITY: 0.001% max

Contextual Info: TLV5619ĆEP 2.7 V TO 5.5 V 12ĆBIT PARALLEL DIGITALĆTOĆANALOG CONVERTER WITH POWER DOWN ą SGLS124A − JULY 2002 − REVISED DECEMBER 2003 D Controlled Baseline D D D D D D D D D D D D D D D applications − One Assembly/Test Site, One Fabrication Site

Contextual Info: TLC1542ĆEP, TLC1543ĆEP 10ĆBIT ANALOGĆTOĆDIGITAL CONVERTERS WITH SERIAL CONTROL AND 11 ANALOG INPUTS SGLS152A − JANUARY 2004 − REVISED FEBRUARY 2006 D Controlled Baseline D D D D D D D D D D D D D DW PACKAGE TOP VIEW − One Assembly/Test Site, One Fabrication

Contextual Info: SN65HVD50-SN65HVD55 www.ti.com SLLS666E – SEPTEMBER 2005 – REVISED OCTOBER 2009 HIGH OUTPUT FULL-DUPLEX RS-485 DRIVERS AND RECEIVERS Check for Samples :SN65HVD50-SN65HVD55 • • • • • • • • 1 1/8 Unit-Load Option Available (Up to 256 Nodes on the Bus)