Not Available
Abstract: No abstract text available
Text: FAST PAGE MODE 150994944-BIT (16777216- WORD BY 9-BIT) DYNAMIC RAM DESCRIPTION The M H16M 09ASD P is 1 , FAST PAGE MODE 150994944-BIT (16777216- WORD BY 9-BIT) DYNAMIC RAM RAS-only refresh, and , PAGE MODE 150994944-BIT (16777216- WORD BY 9-BIT) DYNAMIC RAM Conditions W ith respect to Vss , -BIT (16777216- WORD BY 9-BIT) DYNAMIC RAM SWITCHING CHARACTERISTICS (Ta = 0 ~ 7 0 *C , Vcc = 5V ± 10% , Vss = , after RAS high Column address to RAS hold time Parameter FAST PAGE MODE 150994944-BIT (16777216- WORD
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MH16M09ASDP-5
MH16M09ASDP-6
MH16M09ASDP-7
16100A
150994944-BIT
16777216-WORD
09ASD
MH16M09ASDP
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1998 - 1kx16
Abstract: diode wb1 SCR table TK 69 TSOP
Text: MITSUBISHI LSIs M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M- WORD BY 16-BIT) CACHED DRAM WITH 16K (1024- WORD BY 16-BIT) SRAM Preliminary This document is a preliminary Target Spec. and some of , . 2. The M5M4V16169DTP/RT is a 16M-bit Cached DRAM which integrates input registers, a 1,048,576- word by 16-bit dynamic memory array and a 1024- word by 16-bit static RAM array as a Cache memory (block , M5M4V16169DTP/RT-7,-8,-10,-15 16MCDRAM:16M(1M- WORD BY 16-BIT) CACHED DRAM WITH 16K (1024- WORD BY 16-BIT) SRAM
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M5M4V16169DTP/RT-7
16MCDRAM
16-BIT)
1024-WORD
M5M4V16169DTP/RT
16M-bit
576-word
16-bit
1kx16
diode wb1
SCR table
TK 69 TSOP
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Not Available
Abstract: No abstract text available
Text: MITSUBISHI LSIs M 5 M 4 V 1 6 1 6 9 T P - 1 0 ,- 1 2 ,- 1 5 16M CDRAM16M(1024K- WORD BY 16-BIT)CACHED DRAM WITH 16K(1024- WORD BY 16-BIT)SRAM DESCRIPTION The M5M4V16169TP is a 16M-bit Cached DRAM which integrates input registers, a 1048576- word by 1 6 - bit dynamic memory array and a 1024- word by , MITSUBISHI LSlS M5M4V16169TP-10,-12,-15 16M CDRAM 16M(1024K- WORD BY 16-BIT)CACHED DRAM WITH 16K(1024- WORD , MITSUBISHI LSIs M5M4V16169TP-10,-12,-15 16M CDRAM 16M(1024K- WORD BY 16-BIT)CACHED DRAM WITH 16K(1024- WORD
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CDRAM16M
1024K-WORD
16-BIT
1024-WORD
M5M4V16169TP
16M-bit
1048576-word
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1999 - sharp LRS1331 1999
Abstract: LRS1331 SCE1 SCE2
Text: LRS1331 Stacked Chip 16M Flash Memory and 4M SRAM Data Sheet FEATURES Thirty-one 32K- word , Enhanced automated suspend options Word write suspend to read Block erase suspend to word write , and F-VCCW pin): Read: 25 mA (tCYCLE = 200 ns) Word write: 57 mA Block erase: 42 mA , architecture Two 4K- word boot blocks Six 4K- word parameter blocks · SRAM Access time (MAX.): 85 ns , Down Input (Flash) Block erase and Word Write: VIH Read: VIH Deep Power Down: VIL Input F-WP
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LRS1331
32K-word
72-ball
SMA99087
sharp LRS1331 1999
LRS1331
SCE1
SCE2
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as011
Abstract: AD411 wt246
Text: ,-15 Oct 26,1992 16MCDRAM:16M (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096- WORD BY4 -BIT , (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096-WQRD BY4 -BIT) SRAM BLOCK DIAGRAM vcc vss , ,-12,-15 Oct 26,1992 16MCDRAM:16M (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096-WQRD BY4 , LSIs M5M4V16409ATP-8,-10,-12,-15 O d 26,1992 16MCDRAM:16M (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096- WORD BY4 -BIT) SRAM D a ta T ra n s fe r B u ffe r X fe r M a s k DTBW DTBR Tem po T
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M5M4V16409ATP-8r
16MCDRAM
4096-WORD
MDS-CDRAM-07-12/92/-IK
as011
AD411
wt246
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1999 - Not Available
Abstract: No abstract text available
Text: 32K- word main blocks Top/Bottom boot location versions Extended cycling capability 100,000 block erase cycles Enhanced automated suspend options Word write suspend to read Block erase suspend to word write Block erase suspend to read · Flash Memory and SRAM · Stacked Die Chip Scale , current for F-VCC pin Read: 25 mA (tCYCLE = 200 ns) Word write: 17 mA Block erase: 17 mA Deep , 0.2 V) Optimized array blocking architecture Two 4K- word boot blocks Six 4K- word parameter
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LRS1341/LRS1342
32K-word
72-ball
FBGA072-P-0811)
SMA99092
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Not Available
Abstract: No abstract text available
Text: 16MCDRAM-.16M (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4Q96- WORD BY4 -BIT) SRAM Preliminary This , (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096-WQRD BY4 -BIT) SRAM BLOCK DIAGRAM vcc vss , ) MITSUBISHI LSIs M5M4V16409ATP-8,-10,-12,-15 Oct 26,1992 16MCDRAM:16M (4194304 - WORD BY 4 - BIT) Cache , :16M (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096- WORD BY4 -BIT) SRAM D a ta T r a n s fe r , -8,-10,-12,-15 Oct 26,1992 16MCDRAM:16M (4194304 - WORD BY 4 - BIT) Cache DRAM with 16k (4096-WQRD BY4
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M5M4V16409ATP-8
16MCDRAM-
4Q96-WORD
MDS-CDRAM-07-12/92/-IK
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TAG 107e 400
Abstract: BUS65 MIL-STD-1760B
Text: , providing superior word error rate and zero crossing distortion tolerance. The Busy, Service Request, and Subsystem Flag RT Status Word bits are provided as discrete pins, allowing for easy access by the subsystem , , STATUS, AND BIT WORD Note: Transformers are external FIGURE 1. BUS-65153 BLOCK DIAGRAM © 1991 ILC , from the M id-Parity crossing of the Transm it Com mand word to the M id-Sync crossing of the Transm itting RT Status word . (9) Current drain is for total hybrid (e.g., +5V supply current includes the sum
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BUS-65153
MIL-STD-1553B,
MIL-STD-1760B
-1553B
70-pin
BUS-65153
B-2203,
LPB-5002,
LPB-5009,
TAG 107e 400
BUS65
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ca3f
Abstract: No abstract text available
Text: ) MH16M09AJ-6,-7/ MH16M09ACJ-6.-7 'S FAST PAGE MODE 150994944-BIT (16777216- WORD BY 9-BIT) DYNAMIC RAM DESCRIPTION The M H 1 6 M 09 A J/A C J is 167772 16- word by 9-bit dynamic RAM and consists of nine industly , - WORD I3Y 9-BIT) DYNAMIC RAM DESCRIPTION "he M H 1 6 M 0 9 A T J /A TJA is 1 6 7 7 7 2 1 6 - word by 9 , MODULE) FAs t p a g e m ode i 50994944-BiT (16777216- WORD BY 9-BIT) DYNAMIC RAM and RAS-only , MODE 150994944-BIT (16777216- WORD BY 9-BIT) DYNAMIC RAM (T a = 0 ~ 7 0 * C , V cc = 5 V ± 1 0 % , V
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16MX9
MH16M09AJ-6
MH16M09AJ-7
MH16M09AC
MH16M09ACJ-7
MH16M09ATJ-6
MH16M09ATJ-7
H16M09AT
MH16M09ATJA-7
M5M4161OOAJ
ca3f
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mitsubishi cdram
Abstract: M5M4V16169TP-10
Text: MITSUBISHI LSIs M 5 M 4 V 1 6 1 6 9 T P -1 0 ,-1 2 ,-1 5 16M CDRAM16M(1024K- WORD BY 16-BIT)CACHED DRAM WITH 16K(1024- WORD BY 16-BIT)SRAM DESCRIPTION The M 5 M 4 V 1 6 1 6 9 T P is a 1 6 M -b it , CDRAM 16M(1024K- WORD BY 16-BIT)CACH1D DRAM WITH 16K(1024- WORD BY 16-BIT)SRAM BLOCK DIAGRAM 1 , -BIT)CACHED DRAM WITH 16K(1Q24- WORD BY 16-BIT)SRAM BLOCK DIAGRAM 2 2-56 MITSUBISHI ELECTRIC D a t , MITSUBISHI LSIs M5M4V16169TP-10,-12,-15 16M CDRAM 16M(1024K- WORD BY t6-BIT)CACHEP DRAM WITH 16K(1024- WORD
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CDRAM16M
1024K-WORD
16-BIT
1024-WORD
mitsubishi cdram
M5M4V16169TP-10
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Not Available
Abstract: No abstract text available
Text: 16M (2-BANK x 524288- WORD x 16-BIT) Synchronous DRAM Some of contents are subjected to change without notice. PIN CONFIGURATION (TOP VIEW) DESCRIPTION The M5M4V16S40CTP is a 2-bank x 524288- word x 16 , 0, -12, -1 5 Aprii â 97 16M (2-BANK x 524288- WORD x 16-BIT) Synchronous DRAM BLOCK , ) M 5 M 4 V 1 6 S 4 0 C T P -1 0, -12, -1 5 Aprii â 97 16M (2-BANK x 524288- WORD x 16 , 16M (2-BANK x 524288- WORD x 16-BIT) Synchronous DRAM BASIC FUNCTIONS The M5M4V16S40CTP provides
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524288-WORD
16-BIT)
M5M4V16S40CTP
16-bit
100MHz,
44chronous
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1999 - Not Available
Abstract: No abstract text available
Text: F-VCCW pin): Read: 25 mA (tCYCLE = 200 ns) Word write: 57 mA Block erase: 42 mA Standby current , Two 4K- word boot blocks Six 4K- word parameter blocks Stacked Chip 16M Flash Memory and 4M SRAM Thirty-one 32K- word main blocks Bottom boot location Extended cycling capability 100,000 block erase cycles Enhanced automated suspend options Word write suspend to read Block erase suspend to word , (Flash) Block erase and Word Write: VIH Read: VIH Deep Power Down: VIL Write Protect Input (Flash) Two
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LRS1331
72-ball
32K-word
SMA99087
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2001 - 48-PIN
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128000AL 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD , mode. High level : WORD mode (8M- word by 16-bit) Low level : BYTE mode ( 16M-word by 8-bit) A0 to , . BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 bits of total 24 bits of address , significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8-bit) 8 bits data outputs to O0 to O7 and , ) The most significant output data bus (O15). BYTE mode ( 16M-word by 8-bit) The least significant
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PD23C128000AL
128M-BIT
16M-WORD
16-BIT
PD23C128000AL
48-pin
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2002 - 23c128
Abstract: 48-PIN
Text: -BIT MASK-PROGRAMMABLE ROM 16M-WORD BY 8-BIT (BYTE MODE) / 8M- WORD BY 16-BIT ( WORD MODE) PAGE ACCESS MODE , level : BYTE mode ( 16M-word by 8-bit) A0 to A22 Input (Address inputs) Address input pins , to A22 are used as 23 bits address signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the , data outputs to O0 to O14. (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8 , -bit) (Data output 15, LSB Address input) The most significant output data bus (O15). BYTE mode ( 16M-word
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PD23C128040BL,
23C128080BL
128M-BIT
16M-WORD
16-BIT
PD23C128040BL
PD23C128080BL
44-pin
23c128
48-PIN
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1999 - Not Available
Abstract: No abstract text available
Text: 32K- word main blocks Top/Bottom boot location versions Extended cycling capability 100,000 block erase cycles Enhanced automated suspend options Word write suspend to read Block erase suspend to word write Block erase suspend to read · Flash Memory and SRAM · Stacked Die Chip Scale , current for F-VCC pin Read: 25 mA (tCYCLE = 200 ns) Word write: 17 mA Block erase: 17 mA Deep , 0.2 V) Optimized array blocking architecture Two 4K- word boot blocks Six 4K- word parameter
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LRS1341/LRS1342
32K-word
72-ball
FBGA072-P-0811)
J63428
SMA99092
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2002 - Not Available
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128000BL 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD BY , level : BYTE mode ( 16M-word by 8-bit) A0 to A22 (Address inputs) Input Address input pins. A0 to A22 are , as 23 bits address signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 bits of , O14. (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8-bit) 8 bits data , -bit) The most significant output data bus (O15). BYTE mode ( 16M-word by 8-bit) The least significant
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PD23C128000BL
128M-BIT
16M-WORD
16-BIT
PD23C128000BL
44-pin
48-pin
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1996 - M5M4V16S20CTP
Abstract: M5M4V16s30 M5M4V16S30CTP M5M4V16S20
Text: 2097152- WORD x 4-BIT) Synchronous DRAM Some of contents are subject to change without notice , ) The M5M4V16S20CTP is a 2-bank x 2097152- word x 4-bit Synchronous DRAM, with LVTTL interface. All , 2097152- WORD x 4-BIT) Synchronous DRAM BLOCK DIAGRAM DQ0-7(0-3) I/O Buffer Memory Array , Jan. '97 16M (2-BANK x 2097152- WORD x 4-BIT) Synchronous DRAM PIN FUNCTION CLK Input , 16M (2-BANK x 2097152- WORD x 4-BIT) Synchronous DRAM BASIC FUNCTIONS The M5M4V16S20CTP provides
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M5M4V16S20CTP-10,
2097152-WORD
100MHz
83MHz
67MHz
/64ms
400-mil,
44-pin
44pin
M5M4V16S20CTP
M5M4V16s30
M5M4V16S30CTP
M5M4V16S20
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2003 - 44-PIN
Abstract: 48-PIN
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128000BL 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD , mode ( 16M-word by 8-bit) A0 to A22 Input (Address inputs) Address input pins. A0 to A22 , used as 23 bits address signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 , data outputs to O0 to O14. (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8 , by 16-bit) LSB Address input) The most significant output data bus (O15). BYTE mode ( 16M-word
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PD23C128000BL
128M-BIT
16M-WORD
16-BIT
PD23C128000BL
44-pin
48-pin
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M5M4V16s30
Abstract: No abstract text available
Text: 2097152- WORD x 4-BIT) Synchronous DRAM Some of contents are subject to change without notice. DESCRIPTION The M5M4V16S20CTP is a 2-bank x 2097152- word x 4-bit Synchronous DRAM, with LVTTL interface , -BANK x 2097152- WORD x 4-BIT) Synchronous DRAM BLOCK DIAGRAM 1 dqo -7(o-3) I/O Buffer à , 2097152- WORD x 4-BIT) Synchronous DRAM PIN FUNCTION CLK Input Master Clock: All other inputs are , MITSUBISHI LSIs SDRAM (Rev. 1.0) Jan. '97 M5M4V16S20CTP-10, -12, -15 16M (2-BANK x 2097152- WORD x 4
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M5M4V16S20CTP-10,
2097152-WORD
M5M4V16S20CTP
100MHz,
100MHz
83MHz
67MHz
M5M4V16s30
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2002 - 44-PIN
Abstract: 48-PIN
Text: 16M-WORD BY 8-BIT (BYTE MODE) / 8M- WORD BY 16-BIT ( WORD MODE) Description The µPD23C128000BL is a , BYTE mode. High level : WORD mode (8M- word by 16-bit) Low level : BYTE mode ( 16M-word by 8-bit) A0 , signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 bits of total 24 bits of , . (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8-bit) 8 bits data outputs , Address input) The most significant output data bus (O15). BYTE mode ( 16M-word by 8-bit) The least
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PD23C128000BL
128M-BIT
16M-WORD
16-BIT
PD23C128000BL
44-pin
48-pin
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2002 - Not Available
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128000BL 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD BY , 16-bit) Low level : BYTE mode ( 16M-word by 8-bit) A0 to A22 (Address inputs) Input Address input pins , to A22 are used as 23 bits address signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the , outputs to O0 to O14. (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8-bit) 8 , (8M- word by 16-bit) The most significant output data bus (O15). BYTE mode ( 16M-word by 8-bit) The
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PD23C128000BL
128M-BIT
16M-WORD
16-BIT
PD23C128000BL
44-pin
48-pin
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2000 - Not Available
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128040L 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD , BYTE mode. High level : WORD mode (8M- word by 16-bit) Low level : BYTE mode ( 16M-word by 8-bit) A0 , signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 bits of total 24 bits of , . (The most significant bit (O15) combined to Aâ1.) BYTE mode ( 16M-word by 8-bit) 8 bits data outputs , -bit) LSB Address input) The most significant output data bus (O15). BYTE mode ( 16M-word by 8-bit) The
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PD23C128040L
128M-BIT
16M-WORD
16-BIT
PD23C128040L
48-pin
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1999 - 48-PIN
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128040L 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD BY , BYTE mode. High level : WORD mode (8M- word by 16-bit) Low level : BYTE mode ( 16M-word by 8-bit) A0 , signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 bits of total 24 bits of , . (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8-bit) 8 bits data outputs , Address input) The most significant output data bus (O15). BYTE mode ( 16M-word by 8-bit) The least
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PD23C128040L
128M-BIT
16M-WORD
16-BIT
PD23C128040L
48-pin
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1998 - uPD23C128040LGY-xxx-MKH
Abstract: UPD23C128040LGY-MJH
Text: 16M-WORD BY 8-BIT (BYTE MODE) / 8M- WORD BY 16-BIT ( WORD MODE) PAGE ACCESS MODE Description The , . High level : WORD mode (8M- word by 16-bit) Low level : BYTE mode ( 16M-word by 8-bit) A0 to A22 (Address , by 16-bit) A0 to A22 are used as 23 bits address signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are , data outputs to O0 to O14. (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8 , . WORD mode (8M- word by 16-bit) The most significant output data bus (O15). BYTE mode ( 16M-word by 8
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PD23C128040L
128M-BIT
16M-WORD
16-BIT
PD23C128040L
48-pin
uPD23C128040LGY-xxx-MKH
UPD23C128040LGY-MJH
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1999 - Not Available
Abstract: No abstract text available
Text: DATA SHEET MOS INTEGRATED CIRCUIT µ PD23C128000L 128M-BIT MASK-PROGRAMMABLE ROM 16M-WORD BY , level : BYTE mode ( 16M-word by 8-bit) · A0 to A22 (Address inputs) Address input pin. A0 to A22 , used as 23 bits address signals. BYTE mode ( 16M-word by 8-bit) A0 to A22 are used as the upper 23 bits , outputs to O0 to O14. (The most significant bit (O15) combined to A-1.) BYTE mode ( 16M-word by 8-bit) 8 , mode. WORD mode (8M- word by 16-bit) The most significant output data bus (O15). BYTE mode ( 16M-word by
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PD23C128000L
128M-BIT
16M-WORD
16-BIT
PD23C128000L
48-pin
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