2004 - Not Available
Abstract: No abstract text available
Text: IS42S46400A (4- bank x 16,777,216 - word x 4-bit) IS42S83200A (4- bank x 8,388,608 - word x 8-bit) IS42S16160A (4- bank x 4,194,304 - word x 16-bit) ISSI ® 256 Mb Synchronous DRAM AUGUST 2004 DESCRIPTION IS42S46400A is organized as 4- bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and IS42S83200A is organized as 4- bank x 8,388,608-word x 8-bit and IS42S16160A is organized as 4- bank x 4,194, 304-word x 16-bit. All inputs and outputs are referenced to the rising edge of
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IS42S46400A
IS42S83200A
IS42S16160A
16-bit)
IS42S46400A
216-word
IS42S83200A
608-word
IS42S16160A
304-word
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2004 - Not Available
Abstract: No abstract text available
Text: IS42S46400A (4- bank x 16,777,216 - word x 4-bit) IS42S83200A (4- bank x 8,388,608 - word x 8-bit) IS42S16160A (4- bank x 4,194,304 - word x 16-bit) ISSI AUGUST 2004 ® 256 Mb Synchronous DRAM DESCRIPTION IS42S46400A is organized as 4- bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and IS42S83200A is organized as 4- bank x 8,388,608-word x 8-bit and IS42S16160A is organized as 4- bank x 4,194, 304-word x 16-bit. All inputs and outputs are referenced to the rising edge of
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IS42S46400A
IS42S83200A
IS42S16160A
16-bit)
IS42S46400A
216-word
IS42S83200A
608-word
IS42S16160A
304-word
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M/AS4C16M16S
Abstract: No abstract text available
Text: MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4- bank , Input Bank Activate: BA0, BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D A0-A12 Input , available in the respective bank . During a Precharge command, A10 is sampled to determine if all banks are , command decoder. All commands are masked when CS# is sampled HIGH. CS# provides for external bank
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AS4C16M16S
256Mb
16-bit
cycles/64ms
AS4C16M16S-5TCN
AS4C16M16S-6TCN
AS4C16M16S-6TIN
AS4C16M16S-7TCN
AS4C16M16S-7BCN
M/AS4C16M16S
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a2v28s40
Abstract: A2V28S MIRA SDRAM p2v28s40dtp sdram 4 bank 4096 16 P2V28S20ATP-7 P2V28S20DTP-7 P2V28S30ATP-7 P2V28S40ATP-7 a2v28s40atp
Text: 128Mb Synchronous DRAM P2V28S20ATP-7,-75,-8 (4- BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4- BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4- BANK x 2,097,152-WORD x 16 , :886-2-25174575 JULY.2000 Rev.2.2 128Mb Synchronous DRAM P2V28S20ATP-7,-75,-8 (4- BANK x 8,388,608-WORD x 4-BIT) P2V28S30ATP-7,-75,-8 (4- BANK x 4,194,304-WORD x 8-BIT) P2V28S40ATP-7,-75,-8 (4- BANK x 2 , P2V28S40ATP-7,-75,-8 PRELIMINARY (4- BANK x 8,388,608-WORD x 4-BIT) (4- BANK x 4,194,304-WORD x 8-BIT) (4- BANK
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128Mb
P2V28S20ATP-7
608-WORD
P2V28S30ATP-7
304-WORD
P2V28S40ATP-7
152-WORD
16-BIT)
P2V28S20DTP-7
a2v28s40
A2V28S
MIRA SDRAM
p2v28s40dtp
sdram 4 bank 4096 16
a2v28s40atp
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sdram 1m x 4x 32
Abstract: EM636165 EM636165TS
Text: power Internal pipelined architecture 512K word x 16-bit x 2- bank Programmable Mode registers - CAS , CELL ARRAY ( BANK #0) Sense Amplifier COLUMN COUNTER DQs Buffer A11 ADDRESS BUFFER MODE , ARRAY ( BANK #1) Column Decoder 3 Rev. 3.1 Jul. 2007 EtronTech 1M x 16 SDRAM , Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge command is , ) to select one location out of the 256K available in the respective bank . During a Precharge command
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EM636165
Jul/2007)
16-bit
cycles/32ms
50-pin
60-ball,
1Mx16
60-Ball
sdram 1m x 4x 32
EM636165
EM636165TS
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EM636165
Abstract: No abstract text available
Text: low power Internal pipelined architecture 512K word x 16-bit x 2- bank Programmable Mode registers , CONTROL SIGNAL GENERATOR 2048 X 256 X 16 CELL ARRAY ( BANK #0) Sense Amplifier COLUMN COUNTER , Decoder A0 DQ0 DQ15 2048 X 256 X 16 CELL ARRAY ( BANK #1) Column Decoder 3 Rev. 3.2 , , providing low standby power. A11 Input Bank Select: A11(BS) defines to which bank the BankActivate , respective bank . During a Precharge command, A10 is sampled to determine if both banks are to be precharged
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EM636165
16-bit
cycles/64ms
50-pin
60-ball,
1Mx16
60-Ball
EM636165
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EM636165
Abstract: EM636165TS be55g
Text: architecture 512K word x 16-bit x 2- bank Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst , X 256 X 16 CELL ARRAY ( BANK #0) Sense Amplifier COLUMN COUNTER DQs Buffer A0 A11 , 2048 X 256 X 16 CELL ARRAY ( BANK #1) Column Decoder Preliminary 3 Rev. 2.7 Mar. 2006 , Input Bank Select: A11(BS) defines to which bank the BankActivate, Read, Write, or BankPrecharge , Precharge) to select one location out of the 256K available in the respective bank . During a Precharge
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EM636165
16-bit
cycles/64ms
50-pin
60-bax
1Mx16
60-Ball
EM636165VE
EM636165BE
EM636165
EM636165TS
be55g
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2004 - p2v56s
Abstract: No abstract text available
Text: : 886-2-2517-4575 http: // www.deutron.com.tw 256Mb Synchronous DRAM 256Mb Synchronous DRAM P2V56S20BTP (4- BANK x 16,777,216-WORD x 4-BIT) P2V56S30BTP (4- BANK x 8,388,608-WORD x 8-BIT) P2V56S40BTP (4- BANK x 4 , Synchronous DRAM 256Mb Synchronous DRAM P2V56S20BTP (4- BANK x 16,777,216-WORD x 4-BIT) P2V56S30BTP (4- BANK x 8,388,608-WORD x 8-BIT) P2V56S40BTP (4- BANK x 4,194,304-WORD x 16-BIT) P2V56S20BTP P2V56S30BTP P2V56S40BTP PRELIMINARY (4- BANK x 16,777,216-WORD x 4-BIT) (4- BANK x 8,388,6084-WORD x 8
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256Mb
P2V56S20BTP
P2V56S30BTP
P2V56S40BTP
216-WORD
608-WORD
p2v56s
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2012 - Not Available
Abstract: No abstract text available
Text: : 200/166/143 MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4- bank , modes, providing low standby power. BA0,BA1 Input Bank Activate: BA0, BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D A0-A12 Input Address Inputs: A0-A12 are sampled during the , Precharge) to select one location out of the 4M available in the respective bank . During a Precharge
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AS4C16M16S
256Mb
16-bit
AS4C16M16S-6TCN
AS4C16M16S-6TIN
AS4C16M16S-7TCN
AS4C16M16S-7BCN
AS4C16M16S-6BIN
16M16S
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2012 - Not Available
Abstract: No abstract text available
Text: : 200/166/143 MHz Fully synchronous operation Internal pipelined architecture 4M word x 16-bit x 4- bank , modes, providing low standby power. BA0,BA1 Input Bank Activate: BA0, BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D A0-A12 Input Address Inputs: A0-A12 are sampled during the , Precharge) to select one location out of the 4M available in the respective bank . During a Precharge
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AS4C16M16S
256Mb
16-bit
AS4C16M16S-6TCN
AS4C16M16S-6TIN
AS4C16M16S-7TCN
AS4C16M16S-7BCN
AS4C16M16S-6BIN
16M16S
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Multi Chip Memory
Abstract: 66-ball F0000H-F7FFFH
Text: program or erase cycle completion · Read While Write Operation between Bank I, Bank II, Bank III, Bank , Auto program for Bank I (4Mb) and Bank II (4Mb) - Word Programming (1 word) - Page Programming (128 word) · Auto program for Bank III (12Mb) and Bank IV (12Mb) - Page programming (128 word) · Auto , banks of Bank I, BankII, Bank III and Bank IV. The device offers access times of 70ns/90ns, and a low , , SRAM/85ns Flash Bank I : 2 x 4K Word Boot 6 x 4K Word Parameter 7 x 32K Word Main Bank II : 8
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MX69LW3221/3241T/B
32M-BIT
70/90ns
70/85ns
PM0924
SEP/16/2002
Multi Chip Memory
66-ball
F0000H-F7FFFH
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2004 - Not Available
Abstract: No abstract text available
Text: IS42S46400A (4- bank x 16,777,216 - word x 4-bit) IS42S83200A (4- bank x 8,388,608 - word x 8-bit) IS42S16160A (4- bank x 4,194,304 - word x 16-bit) ISSI AUGUST 2004 ® 256 Mb Synchronous DRAM DESCRIPTION IS42S46400A is organized as 4- bank x 16,777,216-word x 4-bit Synchronous DRAM with LVTTL interface and IS42S83200A is organized as 4- bank x 8,388,608-word x 8-bit and IS42S16160A is organized as 4- bank x 4,194, 304-word x 16-bit. All inputs and outputs are referenced to the rising edge of
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IS42S46400A
IS42S83200A
IS42S16160A
16-bit)
IS42S46400A
216-word
IS42S83200A
608-word
IS42S16160A
304-word
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EM639165TS-6G
Abstract: EM639165TS MX16 EM639165TS-7G EM639165TS7G EM639165 EM639165TS-6LG
Text: MHz Fully synchronous operation Internal pipelined architecture 2M word x 16-bit x 4- bank , ~ A11 BA0 BA1 2 MX16 CELL ARRAY ( BANK #A) De co der ADDRESS BUFFER DQ0 | DQ15 2 MX16 CELL ARRAY ( BANK #B) Column Decoder REFRESH COUNTER De co der 2 MX16 CELL ARRAY ( BANK #C) Column Decoder De co der 2 MX16 CELL ARRAY ( BANK #D) Column Decoder 2 Rev , , providing low standby power. BA0,BA1 Input Bank Select: BA0,BA1 input select the bank for
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EM639165
16-bit
cycles/64ms
54-pin
EM639165
EM639165TS-6G
EM639165TS
MX16
EM639165TS-7G
EM639165TS7G
EM639165TS-6LG
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AS4C16M16S-6TIN
Abstract: AS4C16M16S
Text: synchronous operation Internal pipelined architecture 4M word x 16-bit x 4- bank Programmable Mode registers , , providing low standby power. BA0,BA1 Input Bank Activate: BA0, BA1 input select the bank for operation. BA1 BA0 Select Bank 0 0 BANK #A 0 1 BANK #B 1 0 BANK #C 1 1 BANK #D A0-A12 Input Address Inputs: A0-A12 are sampled during the BankActivate , ) to select one location out of the 4M available in the respective bank . During a Precharge command
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AS4C16M16S
256Mb
16-bit
cycles/64ms
AS4C16M16S-5TCN
AS4C16M16S-6TCN
AS4C16M16S-6TIN
AS4C16M16S-6TIN
AS4C16M16S
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2012 - Not Available
Abstract: No abstract text available
Text: synchronous operation Internal pipelined architecture 4M word x 16-bit x 4- bank Programmable Mode registers - , CLK, are disabled during Power Down and Self Refresh modes, providing low standby power. Bank Activate: BA0, BA1 input select the bank for operation. BA1 0 0 1 1 A0-A12 Input BA0 0 1 0 1 Select Bank BANK #A BANK #B BANK #C BANK #D CKE Input BA0,BA1 Input Address Inputs: A0-A12 are sampled , defining Auto Precharge) to select one location out of the 4M available in the respective bank . During a
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AS4C16M16S
256Mb
16-bit
cycles/64ms
54-pin
AS4C16M16S
AS4C16M16S-5TCN
AS4C16M16S-6TCN
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2003 - Not Available
Abstract: No abstract text available
Text: : 886-2-2517-4575 http: // www.deutron.com.tw 64Mb Synchronous DRAM P2V64S20DTP ( 4- BANK x 4,194,304-WORD x 4-BIT) P2V64S30DTP (4- BANK x 2,097,152-WORD x 8-BIT) P2V64S40DTP (4- BANK x 1,048,576-WORD x 16-BIT) ORDERING , Interface V : LVTTL MIRA DRAM Sep.2003 Rev.2.6 64Mb Synchronous DRAM P2V64S20DTP ( 4- BANK x 4,194,304-WORD x 4-BIT) P2V64S30DTP (4- BANK x 2,097,152-WORD x 8-BIT) P2V64S40DTP (4- BANK x 1,048,576-WORD x 16-BIT) P2V64S20DTP (4- BANK x 4,194,304-WORD x 4-BIT) P2V64S30DTP (4- BANK x 2,097,152
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P2V64S20DTP
P2V64S30DTP
P2V64S40DTP
304-WORD
152-WORD
576-WORD
16-BIT)
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2012 - AS4C16M16S
Abstract: 3MA18 AS4C16M16S-6TCN AS4C16M16S-7BCN AS4C16M16S-5TCN
Text: synchronous operation Internal pipelined architecture 4M word x 16-bit x 4- bank Programmable Mode registers - , standby power. Bank Activate: BA0, BA1 input select the bank for operation. BA1 0 0 1 1 A0-A12 Input BA0 0 1 0 1 Select Bank BANK #A BANK #B BANK #C BANK #D CKE Input BA0,BA1 Input Address , the respective bank . During a Precharge command, A10 is sampled to determine if all banks are to be , masked when CS# is sampled HIGH. CS# provides for external bank selection on systems with multiple banks
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AS4C16M16S
256Mb
16-bit
cycles/64ms
54-pin
AS4C16M16S
AS4C16M16S-5TCN
AS4C16M16S-6TCN
3MA18
AS4C16M16S-7BCN
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GLT51280L16
Abstract: GLT51280L16L
Text: x 16 x 4 (word x bit x bank ), respectively. The synchronous DRAMs achieved high-speed data transfer , cycle · Quad internal banks controlled by BA0 & BA1 ( Bank Select) · Byte control by LDQM and UDQM · , : sales@glink.com.tw TEL : 886-2-27968078 -2- Function DQ Mask Enable Address Input Bank Address Power , Register Row Address Buffer & Burst counter Bank D Bank C Bank B Row Decoder Data Control , Decoder CS Bank A DQ G -LINK GLT51280L16 8M X 16 CMOS Synchronous Dynamic RAM Feb 2004
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GLT51280L16
GLT51280L16
728-bit
166MHz.
54-pin
GLT51280L16L
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GLT5640AL16
Abstract: No abstract text available
Text: 1,048,576 x 16 x 4 (word x bit x bank ), respectively. The synchronous DRAMs achieved high-speed , Possible to assert random column access in every cycle · Quad internal banks controlled by BA0 & BA1 ( Bank , Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ , Bank D Bank C Bank B Row Decoder Data Control Circuit G-Link Technology Corporation, Taiwan , counter Latch Circuit CAS Control Logic RAS Command Decoder CS Bank A DQ G
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GLT5640AL16
GLT5640AL16
864-bit
183MHz.
54-pin
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2001 - MSAB
Abstract: No abstract text available
Text: /80/40)4(BGA) is a four bank Synchronous DRAM organized as 4 banks x 2Mbit x 16, 4 banks x 4Mbit x 8 , Column decoder Sense amplifier & I(O) bus Row decoder Memory array Bank 2 Row decoder Memory array Bank 3 Bank 0 Bank 1 4096 x 512 x 16 bit 4096 x 512 x16 bit Column decoder Sense , Sense amplifier & I(O) bus Row decoder Memory array Bank 1 Row decoder Memory array Bank 2 Row decoder Memory array Bank 3 Bank 0 Column decoder Sense amplifier & I(O) bus 4096 x 1024 x 8 bit
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V54C3128
128Mbit
MSAB
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1999 - VG36641641
Abstract: No abstract text available
Text: · Quad Internal banks controlled by A12 & A13 ( Bank select) · Each Bank can operate simultaneously , Bank select DQM DQ mask enable DQ0 ~ DQ7 DQ0 ~ DQ15 Data - in/data - out (x8) Data - in , Data Control Circuit Rev.3 Input & Output Buffer RAS Bank A Sense Amplifier Control Logic CS Command Decoder Mode Register Bank D Bank C Bank B Row Address Buffer & , One bank active CL = 2 120 110 95 tRC tRC(MIN), Io = 0mA Precharge standby ICC2P current in
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VG366480
1G5-0151
VG36641641
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2003 - IS42S16400A
Abstract: IS42S16400A-10TI
Text: · Internal bank for hiding row access/precharge ® April 2003 OVERVIEW ISSI's 64Mb Synchronous DRAM IS42S16400A is organized as 1,048,576 bits x 16-bit x 4- bank for improved performance. The , DESCRIPTIONS A0-A11 Address Input WE Write Enable BA0, BA1 Bank Select Address LDQM Lower , quad-bank DRAM with a synchronous interface. Each 16,777,216-bit bank is organized as 4,096 rows by 256 , PRECHARGE function enabled. Precharge one bank while accessing one of the other three banks will hide
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IS42S16400A
64-MBIT)
IS42S16400A
16-bit
54-Pin
IS42S16400A-10TI
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2003 - DDR Timing
Abstract: Timing bx0 transistor Eorex
Text: Interleaved Bank Read ( BL=4, CL=3 ) 0 1 2 3 4 5 6 7 8 9 10 11 12 13 , tRRD Bank #0 Bank #1 Active Read tRRD Precharge Active cy0 cy1 cy2 cy3 bx0 bx1 bx2 bx3 Active Read Bank #2 ( Idle ) Bank #3 ( Idle ) 3 tRRD Read Precharge Active eorex DDR Timing Interleaved Bank Read ( BL=4, CL=3, Auto Precharge ) 0 1 2 3 , tDQSCK tDQSCK tDQCK tDQCK tDQSCK DQS tDQCK DQ aw0 aw1 aw2 aw3 tRRD Bank #0
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GLT5640L16P
Abstract: mark code T18
Text: x 16 x 4 (word x bit x bank ), respectively. The synchronous DRAMs achieved high-speed data transfer , to assert random column access in every cycle · Quad internal banks controlled by BA0 & BA1 ( Bank , Mask Enable Address Input Bank Address Power Supply Power Supply for DQ Ground Ground for DQ , Bank D Bank C Bank B Row Decoder Data Control Circuit G-Link Technology Corporation,Taiwan , counter Latch Circuit CAS Control Logic RAS Command Decoder CS Bank A DQ G
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GLT5640L16
GLT5640L16
864-bit
183MHz.
54-pin
GLT5640L16P
mark code T18
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6bx7
Abstract: 6ax7 9t2 transistor EM636165GD-6 EM636165
Text: refresh mode: standard and low power Internal pipelined architecture 512K word x 16-bit x 2- bank , CONTROL SIGNAL GENERATOR 2048 X 256 X 16 CELL ARRAY ( BANK #0) Sense Amplifier COLUMN COUNTER , DQ15 REFRESH COUNTER 2048 X 256 X 16 CELL ARRAY ( BANK #1) Column Decoder 2 Rev. 1.0 , , providing low standby power. A11 Input Bank Select: A11(BS) defines to which bank the BankActivate , respective bank . During a Precharge command, A10 is sampled to determine if both banks are to be precharged
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EM636165
16-bit
cycles/64ms
6bx7
6ax7
9t2 transistor
EM636165GD-6
EM636165
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