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Catalog Datasheet	MFG & Type	PDF	Document Tags
2005 - Not Available Abstract: No abstract text available Text: Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Revision History Rev. No. 1.0 History Initial issue Issue Date Apr. 07, 2005 1 Remark Rev. 1.0 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks DESCRIPTION The CS56A12863 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 2,097, 152x16x4 (word x bit x bank). Synchronous design allows precise cycle controls	Original	PDF	CS56A12863 CS56A12863 152x16x4
2006 - A210 Abstract: CS56A12863 Text: Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks Revision History Rev. No. History Issue Date 1.0 Initial issue Apr. 07, 2005 1.1 Revised DC/AC characteristics Remark Nov. 22, 2006 1 Rev. 1.1 Chiplus reserves the right to change product or specification without notice. Synchronous DRAM CS56A12863 2M Word x 16 Bit x 4 Banks DESCRIPTION The CS56A12863 is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 2,097, 152x16x4 (word x	Original	PDF	CS56A12863 CS56A12863 152x16x4 A210
2001 - uPD45D128164G5-C75-9LG Abstract: uPD45D128442G5-C75-9LG uPD45D128442G5-C80-9LG uPD45D128842G5-C75-9LG uPD45D128842G5-C80-9LG Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The µPD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is compatible	Original	PDF	PD45D128442, 45D128842, 45D128164 45D128164 608x4x4, 304x8x4, 152x16x4 66-pin uPD45D128164G5-C75-9LG uPD45D128442G5-C75-9LG uPD45D128442G5-C80-9LG uPD45D128842G5-C75-9LG uPD45D128842G5-C80-9LG
2001 - EDD1204ALTA-1A Abstract: EDD1204ALTA-75 EDD1204ALTA-7A EDD1208ALTA-1A EDD1208ALTA-75 EDD1208ALTA-7A Material density CDA 195 Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT EDD1204ALTA, EDD1208ALTA, EDD1216ALTA 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The EDD1204ALTA, EDD1208ALTA, EDD1216ALTA are high-speed 134,217,728 bits synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The	Original	PDF	EDD1204ALTA, EDD1208ALTA, EDD1216ALTA EDD1216ALTA 608x4x4, 304x8x4, 152x16x4 66-pin EDD1204ALTA-1A EDD1204ALTA-75 EDD1204ALTA-7A EDD1208ALTA-1A EDD1208ALTA-75 EDD1208ALTA-7A Material density CDA 195
30A120 Abstract: D45128 ATEN 1327 Text: PRELIMINARY DATA SHEET N E C ^ MOS INTEGRATED CIRCUIT _ / /¿ P D 4 5 1 2 8 4 4 1 , 4 5 1 2 8 8 4 1 , 4 5 1 2 8 1 6 3 128 M-bit Synchronous DRAM 4-bank, LVTTL Description The uPD45128441, uPD45128841, uPD45128163 are high-speed 134,217,728 bit synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All	OCR Scan	PDF	uPD45128441 uPD45128841 uPD45128163 608x4x4, 304x8x4, 152x16x4 54-pin 30A120 D45128 ATEN 1327
2001 - C10A Abstract: No abstract text available Text: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442- C10A, 45D128842- C10A, 45D128164- C10A 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The µPD45D128442-C10A, 45D128842-C10A, 45D128164-C10A are high-speed 134,217,728 bits synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The	Original	PDF	PD45D128442- 45D128842- 45D128164- PD45D128442-C10A, 45D128842-C10A, 45D128164-C10A 608x4x4, 304x8x4, 152x16x4 66-pin C10A
1998 - Not Available Abstract: No abstract text available Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The µPD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is	Original	PDF	PD45D128442, 45D128842, 45D128164 45D128164 608x4x4, 304x8x4, 152x16x4 66-pin
D45128841G5-A80 Abstract: No abstract text available Text: PRELIMINARY DATA SHEET / - N E C ^ MOS INTEGRATED CIRCUIT _ / /Â¿ P D 4 5 1 2 8 4 4 1 ,4 5 1 2 8 8 4 1 , 4 5 1 2 8 1 6 3 128 M-bit Synchronous DRAM 4-bank, LVTTL Description The ,uPD45128441, 45128841, 45128163 are high-speed 134,217,728 bit synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous	OCR Scan	PDF	uPD45128441 608x4x4, 304x8x4, 152x16x4 S54G5-80-9JF PD45128441 PD45128xxx. juPD45128xxxG5 54-pin D45128841G5-A80
1997 - Not Available Abstract: No abstract text available Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD45128441,45128841,45128163 128 M-bit Synchronous DRAM 4-bank, LVTTL Description The µPD45128441, 45128841, 45128163 are high-speed 134,217,728 bit synchronous dynamic random-access memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture. All inputs and outputs are synchronized with the positive edge of the clock	Original	PDF	PD45128441 PD45128441, 608x4x4, 304x8x4, 152x16x4 54-pin
1998 - BT146 Abstract: uPD45D128164G5-C12-9LG uPD45D128442G5-C10-9LG uPD45D128442G5-C12-9LG uPD45D128842G5-C10-9LG Text: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The µPD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The synchronous DRAM is	Original	PDF	PD45D128442, 45D128842, 45D128164 45D128164 608x4x4, 304x8x4, 152x16x4 66-pin BT146 uPD45D128164G5-C12-9LG uPD45D128442G5-C10-9LG uPD45D128442G5-C12-9LG uPD45D128842G5-C10-9LG
Not Available Abstract: No abstract text available Text: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT u P D 4 5 D 1 2 8 4 4 2 ,4 5 D 1 2 8 8 4 2 ,4 5 D 1 2 8 1 6 4 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) Description The uPD45D128442, uPD45D128842, uPD45D128164 are high-speed 134,217,728 bits synchronous dynam ic randomaccess memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular	OCR Scan	PDF	uPD45D128442 uPD45D128842 uPD45D128164 608x4x4, 304x8x4, 152x16x4 66-pin T17-T21) T14-T15) T16-T21)
Not Available Abstract: No abstract text available Text: PRELIMINARY DATA SHEET NEC MOS INTEGRATED CIRCUIT UPD45D128442, UPD45D128842, UPD45D128164 128 M-bit Synchronous DRAM with Double Data Rate (4-bank, SSTL_2) D e s c rip tio n The ^¡PD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4194,304x8x4, 2,097, 152x16x4 (word x bit x bank), respectively. The synchronous DRAMs use Double Data Rate (DDR) where data bandwidth is twice of regular synchronous DRAM. The	OCR Scan	PDF	UPD45D128442, UPD45D128842, UPD45D128164 PD45D128442, 45D128842, 45D128164 608x4x4, 304x8x4, 152x16x4 66-pin