14P2N-A MITSUBISHI Search Results

74ls20 mitsubishi

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC20P/FP/DP DUAL 4-INPUT P O S IT IV E NAND GATE DESCRIPTION The M74HC20 is a semiconductor integrated circuit con­ sisting of two 4-input positive-logic NAND gates, usable as negative-logic NOR gates. PIN CONFIGURATION TOP VIEW

Contextual Info: MITSUBISHI HIGH SPEED CMOS M 74H C 03P /F P /D P QUADRUPLE 2-INPUT PO SITIVE NAND GATE W ITH OPEN-DRAIN OUTPUTS DESCRIPTION The M 7 4 H C 0 3 is a s e m ic o n d u c to r in te g r a te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of fo u r 2 -in p u t p o s itiv e -lo g ic N A N D g a te s u s a b le as

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC113P/FP/DP DUAL I -K F L IP -F L O P WITH S E T DESCRIPTION T he M 7 4 H C 1 1 3 is a sem ico n d u cto r integrated circu it co n ­ PIN CON FIGURATIO N TOP VIEW sistin g of of tw o n e g a tiv e -e d g e trig g ered J - K flip flops with

pin DIAGRAM OF IC 74ls30

Abstract: PIN CONFIGURATION OF 74LS30
Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC30P/FP/DP 8-INPUT P O S IT IV E NAND G A TE DESCRIPTION The M 74H C 30 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of an 8-input po sitive -lo g ic NAND gates, usable as n e g a tive -lo g ic NOR gates.

74ls238

Abstract: 74hc238p of 74LS238 74LSTTL
Contextual Info: MITSUBISHI HIGH SPEED CMOS & X0' M 74H C 238P /F P /D P c l-O F -8 DECO D ER/DEM ULTIPLEXER Vit»1" DESCRIPTION PIN CONFIGURATION TOP VIEW The M 74H C 238 is a sem iconductor integrated circuit con­ sisting of a 3 -b it binary-to-octal d e c o d e r/d e m u ltip le x e r with

J-K Flip flops

Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC107P/FP/DP DUAL J-K F L I P - F L O P WITH R E S E T DESCRIPTION The M74HC107 is a semiconductor integrated circuit con­ sisting of two negative-edge triggered J-K flip flops with in­ dependent control inputs PIN CONFIGURATION TOP VIEW

74HC09

Abstract: 20P1N
Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M 74H C 09P /F P /D P Q UADRUPLE 2 -IN P U T P O S IT IV E AND GATE W IT H OPEN-DRAIN O U TPU TS DESCRIPTION The M 74H C 09 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2-input po sitive-lo gic AND gates usable as

12-Bit Parallel-IN Serial-OUT Shift Register

Abstract: M51660L M52770ASP M52778SP M5230L m52760sp M51971L m51957bl series M54640 M65817AFP
Contextual Info: ASSPs ICs for Visual and Audio Equipments ICs for Information and Communication Equipments ICs for Control , Driver and Others General Purpose ICs Preceding Page MITSUBISHI ELECTRIC CORPORATION ICs for Visual and Audio Equipments Sound Processor TV Sets

Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HC279P/FP/DP • AH v,*"w ' V ¡*s Q U AD RU PLE R-S LA TCH D E S C R IP T IO N T he M 7 4 H C 2 7 9 is a sem ico n d u cto r integrated circuit co n ­ PIN C O N F IG U R A T IO N TO P VIEW sistin g of four R -S flip flops.

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC02P/FP/DP QUADRUPLE 2 -IN P U T P O S IT IV E NOR GATE DESCRIPTION T h e M 7 4 H C 0 2 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2-inp ut p o sitive-logic N O R gates, usable as

VT10L

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS M 74H C 132P /FP /D P QUADRUPLE 2 -IN P U T S C H M IT T -T R IG G E R P O S IT IV E NAND GATE DESCRIPTION T h e M 7 4 H C 1 3 2 is a sem iconductor in teg rated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2-inp ut S ch m itt-trig g er positive-logic N A N D

M4066BP

Abstract: M4016BP M4066BFP IVI4066BP IVS4066BP 109fl M4016 10KN 109fi
Contextual Info: M 4066BP SVS4066BFP •« -í • •¡■y v . QUADRUPLE B ILA TE R AL SW ITCH 6249826 MITSUBISHI ^ DESCRIPTION ELEK LINEA R / The M4066BP is a semiconductor integrated circuit consist­ 8 OC 0 9 1 1 7 D PIN CONFIGURATION (TOP VIEW) ~ ing of four independent bilateral analog switches.

Contextual Info: M ITSU B ISH I HIGH SPEED CMOS 9 » s'?60' *. M 74H C T 04 P /F P /D P CV » ^ ' v tfS -Y ' HEX IN V E R TE R W IT H L S T T L -C O M P A T IB L E IN P U T S DESCRIPTION The M 74H C T04 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW

pin configuration ic 74LS21

Abstract: 74LS21 PIN CONFIGURATION PIN CONFIGURATION OF 74LS21 74ls21B Mitsubishi tm
Contextual Info: MITSUBISHI HIGH SPEED CMOS M 74H C 21P/FP/D P DUAL 4-INPUT PO SITIVE AND GATE DESCRIPTION T h e M 7 4 H C 2 1 is a s e m ic o n d u c to r in te g ra te d c irc u it c o n ­ PIN CONFIGURATION TOP VIEW s is tin g of tw o 4 -in p u t p o s itiv e -lo g ic A N D g a te s, u s a b le as

74LS10 mitsubishi

Contextual Info: M IT S U B IS H I HIGH SPEED CMOS M74HC10P/FP/DP T R IP L E 3 -IN P U T P O S IT IV E NAND GATE DESCRIPTION PIN CONFIGURATION TOP VIEW The M74HC10 is a semiconductor integrated circuit con­ sisting of three 3-input positive-logic NAND gates, usable as negative-logic NOR gates.

M4016BP

Abstract: M4066BP 4066bf 4066bp 4066B M4016
Contextual Info: D | bEMTfiSt. □ODTll? 5 MITSUBISHI ELEK {LINEAR} BD M IT S U B IS H I CMOS LOGIC M 4066B P EV84066BFP Q U A D R U PLE B IL A T E R A L S W IT C H 6249826 MITSUBISHI •'!. ELEK LINEAR 7 DESCRIPTION T h e M 4066B P is a semiconductor integrated circuit consist"

Contextual Info: MITSUBISHI <LINEAR ICs> M51924P,FP QUAD COMPARATOR DESCRIPTION The M51924P.FP is a quad four in d ependent com parator and operates over a w id e voltage range from a single supply voltage. Especially the M51924P.FP has superiority as to ch aracteristics of input current (inp u t resistance) and fits to

Contextual Info: MITSUBISHI <LINEAR ICs> M51924PfFP QUAD COMPARATOR DESCRIPTION Th e M 5 1924 P .F P is a q u a d fo u r in d e p e n d e n t c o m p a ra to r PIN CONFIGURATION (TOP VIEW) and o p e ra te s o v e r a w id e v o lta g e ra n g e fro m a s in g le s u p p ly

pin configuration logic symbol 74LS32

Abstract: pin configuration of ic 74ls32 IC PIN CONFIGURATION OF 74LS32
Contextual Info: MITSUBISHI HIGH S P E E D CMOS M 74H C 32P /FP /D P QUADRUPLE 2-INPUT P O S IT IV E OR GATE DESCRIPTION The M 74H C 32 is a sem iconductor integrated circuit con­ PIN CONFIGURATION TOP VIEW sisting of four 2-input po sitive -lo g ic OR gates, usable as

74HC266AP

Abstract: 74HC266A 74LS266 pin configuration
Contextual Info: MITSUBISHI {DGTL LOGIC} 11 !. DËTJ taMTfla? 0013353 3 ., M IT S U B IS H I HIGH SPEED CMOS M74HC266AP/FP/DP 6 2 4 9 82 7 M ITSUBISHI CDGTL LOGIC 91D 13222 D Q U A D R U PLE 2 -IN P U T E X C L U S IV E NOR GATE W IT H OPEN -D R A IN O U T P U T S T ”

20P1N

Abstract: ST 2936
Contextual Info: qv/ M IT S U B IS H I HIGH SPEED CMOS M 74H C 377P/FP/D W P *>»“ •V cv»"6 <»<* OCTAL D -T Y P E F L IP -F L O P W ITH C OM M ON CLOCK AND ENABLE DESCRIPTION The M74HC377 is a sem iconductor integrated c ircu it con­ PIN CONFIGURATION TOP VIEW sisting of eigh t p o s itiv e -e d g e trig g e re d D -type flip flops

IC TTL 74LS00

Abstract: 74ls00 74LS00 gate diagram
Contextual Info: MITSUBISHI HIGH SPEED CMOS M74HCT00P/FP/DP QUADRUPLE 2-INPUT POSITIVE NAND GATE WITH L S TTL-C O M P A TIB LE INPUTS DESCRIPTION The M74HCT00P is a semiconductor integrated circuit con­ sisting of four 2-input positive-logic NAND gates, usable as negative-logic NOR gates.

74hc190p

Abstract: c190p M74HC190P
Contextual Info: MITSUBISHI HIGH S P E E D CMOS M 74H C 190P /FP /D P So'-' cUxC ^ P R E S E T T A B L E BCD U P/DO W N COUNTER DESCRIPTION T h e M 7 4 H C 1 9 0 is a s e m ic o n d u c to r in te g ra te d c irc u it c o n ­ s is tin g of a p re s e tta b le s y n c h ro n o u s

74LS86 pin configuration ic

Abstract: M74HC86P
Contextual Info: MITSUBISHI HIGH S P E E D CMOS M74HC86P/FP/DP QUADRUPLE 2-INPUT E X C L U S IV E OR GATE DESCRIPTION The M 74H C 86 is a sem iconductor integrated c irc u it con­ PIN CONFIGURATION TOP VIEW sisting of fou r 2-input exclusive OR gates. FEATURES • H ig h -sp e e d : 9ns typ. (C L= 1 5 p F , V0C= 5 V )