128MDRAM Search Results

P-TSOPII-54

Abstract: PC133 registered reference design
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • High Performance: • Multiple Burst Read with Single Write Operation -7 -7.5 -8 Units fCK 143 133 125 MHz • Automatic and Controlled Precharge Command tCK3 7 7.5 8 ns • Data Mask for Read/Write Control (x4, x8)

smd marking T22

Abstract: smd transistor marking ba 128M-BIT P-TSOPII-54 P-TSOP-54 PC133 registered reference design 128-MBIT
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)

P-TSOPII-54

Contextual Info: HYB 39S128400/800/160DT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM Preliminary Target Specification 10.01 High Performance: • Multiple Burst Read with Single Write Operation -6 -7 -7.5 -8 Units fCK 166 143 133 125 MHz • Automatic and Controlled Precharge

Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)

smd marking T22

Abstract: PC133-222-520
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • High Performance: • Multiple Burst Read with Single Write Operation -7 -7.5 -8 Units fCK 143 133 125 MHz • Automatic and Controlled Precharge Command tCK3 7 7.5 8 ns • Data Mask for Read/Write Control (x4, x8)

smd CA-Y

Abstract: P-TSOPII-54 smd CAY
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 Units fCK 133 125 MHz tCK3 7.5 8 ns tAC3 5.4 6 ns

HYB 39S128160CT-7

Abstract: HYB 39S128800CT-7 HYB 39S128160CT-7.5
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)