120PS Search Results

ICS93V850

Abstract: TSSOP48
Contextual Info: ICS93V850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps

ncc cap

Abstract: SELIC NLB6205 13D20
Contextual Info: NEL SELIC NLB6205 Quad exclusive OR/NOR D es c rip tio n The NLB6205 is an ultra high-speed monolithic quad exclusive OR/NOR gates. Pin A s s ig n m e n t Top V ie w C era m ic ( F e a tu re s • Typical AC characteristics Data rate up to 4 Gb/s. t=120ps

ICS93705

Abstract: DASF002341
Contextual Info: ICS93705 Integrated Circuit Systems, Inc. DDR Phase Lock Loop Zero Delay Clock Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps

Contextual Info: ICS93732 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • CYCLE - CYCLE jitter 66MHz : <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps

32-PIN

Abstract: SY55856U SY55856UHG SY55856UHGTR SY55856UHI SY55856UHITR
Contextual Info: Micrel, Inc. 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE SuperLite SY55856U SuperLite™ SY55856U FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz fMAX • < 384ps prop delay • < 120ps tr/tf ■ Delay either clock or data

7408 ic diagram

Abstract: IN150 max3827 IN450 d-215 diode
Contextual Info: 19-2144; Rev 0; 8/01 +3.3V, 2.5Gbps Quad Limiting Amplifier Features ♦ Single +3.3V Supply ♦ Single-, Dual-, or Quad-Channel Operation at 2.5Gbps ♦ 700mW Total Power Dissipation Quad-Channel Operation ♦ 120ps Maximum Output Edge Speed ♦ Overall and Individual Channel Loss-of-Power

93732AF

Abstract: DDR4 jedec 93732AFLF
Contextual Info: ICS93732 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • CYCLE - CYCLE jitter 66MHz : <120ps • CYCLE - CYCLE jitter (>100MHz): <65ps

ICS93705

Contextual Info: ICS93705 Integrated Circuit Systems, Inc. DDR Phase Lock Loop Zero Delay Clock Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps

Contextual Info: 2.5V/3.3V 3.0GHZ DUAL 2 x 2 CML CROSSPOINT SWITCH W/INTERNAL TERMINATION SuperLite SY55858U FINAL DESCRIPTION FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz 3Gbps • tr/ tf < 120ps • Within-device skew < 25ps ■ Non-blocking “switch architecture”

Contextual Info: SuperLite SY55856U SuperLite™ 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE Micrel, Inc. SY55856U FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz fMAX • < 384ps prop delay • < 120ps tr/tf ■ Delay either clock or data

Contextual Info: 2.5V/3.3V 3.0GHZ DUAL 2 x 2 CML CROSSPOINT SWITCH W/INTERNAL TERMINATION SuperLite SY55858U DESCRIPTION FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • tr/ tf < 120ps • Within-device skew < 25ps ■ Non-blocking “switch architecture”

Contextual Info: SuperLite 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE Micrel SuperLite™ SY55856U SY55856U FINAL FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz FMAX • < 384ps prop delay • < 120ps Tr/Tf ■ Delay either clock or data

QA-1

Contextual Info: 2.5V/3.3V 3.0GHZ DUAL 2 x 2 CML CROSSPOINT SWITCH W/INTERNAL TERMINATION Micrel SuperLite SY55858U SuperLite™ SY55858U FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz 3Gbps • tr/ tf < 120ps • Within-device skew < 25ps ■ Non-blocking “switch architecture”

5D marking

Abstract: marking code da1 marking DA1 SY55858U SY55858UHI SY55858UHITR
Contextual Info: 2.5V/3.3V 3.0GHZ DUAL 2 x 2 CML CROSSPOINT SWITCH W/INTERNAL TERMINATION SuperLite SY55858U FINAL DESCRIPTION FEATURES • Guaranteed AC parameters over temperature: • fMAX > 3.0GHz • tr/ tf < 120ps • Within-device skew < 25ps ■ Non-blocking “switch architecture”

32-PIN

Abstract: SY55856U SY55856UHG SY55856UHGTR SY55856UHI SY55856UHITR
Contextual Info: Micrel, Inc. 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE SuperLite SY55856U SuperLite™ SY55856U FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz fMAX • < 384ps prop delay • < 120ps tr/tf ■ Delay either clock or data

Contextual Info: 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE SuperLite SY55856U DESCRIPTION FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz FMAX • < 384ps prop delay • < 120ps Tr/Tf ■ Delay either clock or data ■ 50ps increments

IN41

Abstract: MAX3822 MAX3822UCM MAX3825 IN250
Contextual Info: 19-2144; Rev 0; 8/01 +3.3V, 2.5Gbps Quad Limiting Amplifier Features ♦ Single +3.3V Supply ♦ Single-, Dual-, or Quad-Channel Operation at 2.5Gbps ♦ 700mW Total Power Dissipation Quad-Channel Operation ♦ 120ps Maximum Output Edge Speed ♦ Overall and Individual Channel Loss-of-Power

32-PIN

Abstract: SY55856U SY55856UHG SY55856UHGTR SY55856UHI SY55856UHITR
Contextual Info: Micrel, Inc. 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE SuperLite SY55856U SuperLite™ SY55856U FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz fMAX • < 384ps prop delay • < 120ps tr/tf ■ Delay either clock or data

Contextual Info: ICS93V850 Integrated Circuit Systems, Inc. Preliminary Product Preview DDR Phase Lock Loop Clock Driver Recommended Application: DDR Clock Driver Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps

Contextual Info: ICS93722 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps

SY55856U

Abstract: SY55856UHI SY55856UHITR
Contextual Info: 2.5V/3.3V 2.5GHz DIFFERENTIAL 2-CHANNEL PRECISION CML DELAY LINE DESCRIPTION FEATURES • Guaranteed AC parameters over temp and voltage • > 2.5GHz FMAX • < 384ps prop delay • < 120ps Tr/Tf ■ Delay either clock or data ■ 50ps increments ■ ± 350ps total delay

CMD333URC-2

Abstract: CM-1819 CCFL20150 19000251 CMDA30CB15D13L 192C2351 6839BPE
Contextual Info: Statuts as of : 11 July 2006 CML's list of RoHs compliant parts Aviation Incandescent Lamps Part Number ROHS Compliant 120PSB 3071BPEGPL 4009BPE 4009BPEGPL 6839BPE 8-2402 CM1819 CM1820 CM1829 CM1835 CM1864 Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Based LEDs

PYG28

Contextual Info: ICS93722 Integrated Circuit Systems, Inc. Low Cost DDR Phase Lock Loop Zero Delay Buffer Recommended Application: DDR Zero Delay Clock Buffer Pin Configuration Switching Characteristics: • PEAK - PEAK jitter 66MHz : <120ps • PEAK - PEAK jitter (>100MHz): <75ps

Contextual Info: TO -2 20A B PSMN7R8-120PS N-channel 120V 7.9mΩ standard level MOSFET in TO220 25 January 2013 Product data sheet 1. General description Standard level N-channel MOSFET in TO220 package qualified to 175C. This product is designed and qualified for use in a wide range of industrial, communications and power