12 BIT SYNCHRONOUS COUNTER Search Results

Contextual Info: SONY CXK77V3211Q 12/14 32768-word by 32-bit High Speed Synchronous Static RAM Description The CXK77V3211Q is a 32K x 32 high performance synchronous SRAM with a 2-bit burst counter and output register. All synchronous inputs pass through register controlled

TC59S1616

Abstract: TC59S1616AFT TC59S1608AF
Contextual Info: T O S H IB A TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 524,288-WORD X 2 BANK X 16-BIT SYNCHRONOUS DYNAMIC RAM 1,048,576-WORDx2 BANKx8-BIT SYNCHRONOUS DYNAMIC RAM

sv005

Abstract: 74LV161 74LV161PW
Contextual Info: INTEGRATED CIRCUITS 74LV161 Presettable synchronous 4-bit binary counter; asynchronous reset Product specification Supersedes data of 1997 Feb 12 IC24 Data Handbook Philips Semiconductors 1997 May 15 Philips Semiconductors Product specification Presettable synchronous 4-bit binary counter;

CXK77V3211Q

Contextual Info: CXK77V3211Q -12/14 32768-word by 32-bit High Speed Synchronous Static RAM For the availability of this product, please contact the sales office. Description The CXK77V3211Q is a 32K x 32 high performance synchronous SRAM with a 2-bit burst counter and output register. All synchronous inputs pass through

M12179

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT 12:59 µPD431636L 1M-BIT CMOS SYNCHRONOUS FAST SRAM 32K-WORD BY 36-BIT PIPELINED OPERATION Description The µPD431636L is a 32,768-word by 36-bit synchronous static RAM fabricated with advanced CMOS technology

Contextual Info: TOSHIBA TC55V1325FF-7,-8,-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V1325FF is a 1,048,576-bit synchronous pipelined burst static random access memory SRAM

Contextual Info: TO SHIBA TC55V1325FF-7,-8,-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V1325FF is a 1,048,576-bit synchronous pipelined burst static random access memory SRAM

Contextual Info: TO SHIBA TC55V1325FF-7,-8,-10,-12 TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON GATE CMOS 32,768-WORD BY 32-BIT SYNCHRONOUS PIPELINED BURST STATIC RAM DESCRIPTION The TC55V1325FF is a 1,048,576-bit synchronous pipelined burst static random access memory SRAM

Contextual Info: 74HC193-Q100; 74HCT193-Q100 Presettable synchronous 4-bit binary up/down counter Rev. 1 — 12 July 2013 Product data sheet 1. General description The 74HC193-Q100; 74HCT193-Q100 is a 4-bit synchronous binary up/down counter. Separate up/down clocks, CPU and CPD respectively, simplify operation. The outputs

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-11052-1E MEMORY CMOS 4 x 512 K × 32 BIT SYNCHRONOUS DYNAMIC RAM MB811L643242B-10/-12/-15/-10L/-12L/-15L CMOS 4-Bank × 524,288-Word × 32 Bit Synchronous Dynamic Random Access Memory • DESCRIPTION The Fujitsu MB811L643242B is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing

Contextual Info: . TOSHIBA 11\ I I TC55V1325FF-8, TC55V1325FF -10, TC55V1325FF -12 TECHNICAL DATA SILICON G A TE CMOS TENTATIVE 32,768 W O R D x 32 BIT Synchronous Pipelined Burst SRAM DESCRIPTION The TC55V1325FF is a 1,048,576 bit synchronous pipelined burst SRAM that is organized as 32,768

Contextual Info: To Top / Lineup / Index FUJITSU SEMICONDUCTOR DATA SHEET DS05-11052-1E MEMORY CMOS 4 x 512 K × 32 BIT SYNCHRONOUS DYNAMIC RAM MB811L643242B-10/-12/-15/-10L/-12L/-15L CMOS 4-Bank × 524,288-Word × 32 Bit Synchronous Dynamic Random Access Memory • DESCRIPTION

A43L0616BV-7F

Abstract: A43L0616B A43L0616BV
Contextual Info: A43L0616B 512K X 16 Bit X 2 Banks Synchronous DRAM Document Title 512K X 16 Bit X 2 Banks Synchronous DRAM Revision History History Issue Date Remark 0.0 Initial issue May 12, 2003 Preliminary 0.1 Change AC Timing & DC Value February 27, 2006 1.0 Final version release

Contextual Info: SONY CXK77V3211Q-11/12/14 PRELIMINARY D escription The CXK77V3211Q is a 32K x 32 high performance synchronous SRAM with a 2-bit burst counter and output register. All synchronous inputs pass through register controlled by a positive-edge-triggered single clock

MARKING CEK

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET ADVANCE INFO. MEMORY CMOS 4 X 1M X 16 BIT DOUBLE DATA RATE SDRAM MB81P641647A-10/-12 CMOS 4-BANK 1,048,576-WORD x 16 BIT Synchronous Dynamic Random Access Memory with Double Data Rate • DESCRIPTION The Fujitsu MB81P641647A is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing

MARKING CEK

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET ADVANCE INFO. MEMORY CMOS 4 x 4M x 4 BIT DOUBLE DATA RATE SDRAM MB81P64447A-10/-12 CMOS 4-BANK 4,194,304-WORD x 4 BIT Synchronous Dynamic Random Access Memory with Double Data Rate • DESCRIPTION The Fujitsu MB81P64447A is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET ADVANCE INFO. MEMORY CMOS 4 x 2M x 8 BIT DOUBLE DATA RATE SDRAM MB81P64847A-10/-12 CMOS 4-BANK 2,097,152-WORD x 8 BIT Synchronous Dynamic Random Access Memory with Double Data Rate • DESCRIPTION The Fujitsu MB81P64847A is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing

l64324

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET D S 0 5 -1 1 0 5 2 -1 E MEMORY CMOS 4 X 512 K x 32 BIT SYNCHRONOUS DYNAMIC RAM MB811L643242B -10/-12/-15/-10L/-12L/-15L CMOS 4-Bank x 524,288-Word x 32 Bit Synchronous Dynamic Random Access Memory • DESCRIPTION The Fujitsu M B811L643242B is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing

Contextual Info: TC59GJ632AFB-80,-10,-12 TOSHIBA TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT StU CbN ^pN bLIJH IC 262,144-WORDX 2-BANKX32-BIT SYNCHRONOUS GRAPHICS RAM DESCRIPTION The TC59G1632AFB is a CM OS synchronous graphics random access memory or& ajiize^a* 262.144

TC59G1631

Contextual Info: TO SHIBA TC59G1631AFB-80.-10.-12 TENTATIVE TOSHIBA MOS DIGITAL INTEGRATED CIRCUIT SILICON MONOLITHIC 262,144-WORD x 2-BANK x 32-BIT SYNCHRONOUS GRAPHICS RAM DESCRIPTION The TC59G1631AFB is a CMOS synchronous graphics random access memory organized as 262, 144

sdlc schematic

Abstract: IN SDLC PROTOCOL SDLC 000D 001C WR10 Z80185 WR1 marking code
Contextual Info: USER’S MANUAL CHAPTER 12 ESCC 12.1 INTRODUCTION This element of the Z80185 allows serial communications in a variety of modes, including asynchronous start-stop , character-oriented synchronous modes like IBM's Bisync, and bit-oriented synchronous modes like IBM's SDLC,

marking cek

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET ADVANCE INFO. MEMORY CMOS 4 x 2M x 8 BIT DOUBLE DATA RATE SDRAM MB81P64847A-10/-12 CMOS 4-BANK 2,097,152-WORD x 8 BIT Synchronous Dynamic Random Access Memory with Double Data Rate • DESCRIPTION The Fujitsu MB81P64847A is a CMOS Synchronous Dynamic Random Access Memory SDRAM containing

SP8531JN

Abstract: SP8531JS SP8531KN TMS320C26 SP8530 SP8531 voltage regulator 16-Pin 15 Volt KE72
Contextual Info: SP8531 12-Bit Sampling Serial Out Analog to Digital Converter • ■ ■ ■ ■ ■ ■ 12 Bit Resolution Single +5Volt Supply Internal Reference 0 to +2.5 Volt Input Range Fast, 3.75 µs Conversion Time Fast Power Shutdown/Turn-On Mode 3-Wire Synchronous Serial High Speed

HM5216405

Abstract: HM5216405LTT-10H HM5216405TT-10H HM5216405TT-12 HM5216805 HM5216805LTT-10H HM5216805TT-10H HM5216805TT-12 Hitachi DSA00196
Contextual Info: HM5216805 Series, HM5216405 Series 1,048,576-word x 8-bit × 2-bank Synchronous Dynamic RAM 2,097,152-word × 4-bit × 2-bank Synchronous Dynamic RAM ADE-203-304D Z Rev. 4.0 Jun. 12, 1997 Description All inputs and outputs are referred to the rising edge of the clock input. The HM5216805 Series, HM5216405