1025TH Search Results

Contextual Info: SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 x 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 D D D D D D D D D Choice of Memory Organizations

microdisplay

Abstract: The MicroDisplay MD1024G5 MD640 MAX4220 MAX4544 MAX5444 MD640G3 NAIS 210 LED Display Theory
Contextual Info: MD1024G5 Grayscale 1024 x 768 MicroMonitor General Description The MD1024G5 device is an active matrix liquid crystal display with 1024 by 768 spatial resolution. Integrated horizontal and vertical shift registers reduce driving logic. The device is easy to

Contextual Info: Am27S35/Am27S37 8,192-Bit 1024x8 Bipolar Registered PROM with Programmable INITIALIZE Input Versatile programmable asynchronous or synchronous enable for simplified word expansion Buffered common INITIALIZE input either asynchronous (Am27S35) or synchronous (Am27S37)

C0910

Contextual Info: REVISIONS DATE DESCRIPTION LTR APPROVED YR-MO-DA A Changes in accordance with NOR 5962-R231-93. 93-09-21 M. A. Frye B Updated boilerplate. Added device types 03-05. Removed programming requirements from drawing. TABLE I. changes. Editorial changes throughout.

CY7C235A

Contextual Info: CY7C235A / CYPRESS • Features • C M O S for optim um speed/power • H igh speed — 18 ns address set-up — 12 n s clock to output • IK x 8 Registered PROM Slim , 3 00-m il, 24-pin p lastic or h er­ m etic D IP o r 28-pin LCC an d PLCC • SV ± 10% Vc c , com m ercial and

Contextual Info: SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 x 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 D D D D D D D D D Choice of Memory Organizations

MN3307

Abstract: MN3300 fcp 40
Contextual Info: MN3300 Series MN3307 1024-Stage Ultra Low Voltage Operation BBD for Audio Signals • Overview ■ Pin Assignment The MN3307 is a 1024-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3 V supply and provides a signal delay up to 51.2 ms and is suitable

Contextual Info: CY7C235 CYPRESS SEMICONDUCTOR 1024 x 8 Registered PROM Features • CMOS for optimum speed/power • 5V +10% V cc, commercial and military • High speed — 25 ns max set-up — 12 ns dock to output • TTL compatible I/O • Low power — 495 mW commercial

microphone czn-15e

Contextual Info: MN3300 Series MN3305 4096-Stage Ultra Low Voltage Operation BBD for Audio Signals • Overview ■ Pin Assignment The MN3305 is a 4096-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3V supply and provides a signal delay up to 204.8 ms and is suitable

AM27S35

Abstract: AM27S35A CD3024 PD3024 1024x8 PROM
Contextual Info: Am27S35/S35A/Am27S37/S37A _ „ Advanced Micro Devices 8,192-Bit 1024x8 Bipolar Registered PROM with Programmable INITIALIZE Input DISTINCTIVE CHARACTERISTICS • • Slim, 24-pin, 300-mil lateral center package occupies approximately 1/3 the board space required by standard

Contextual Info: SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 x 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 D D D D D D D D D Choice of Memory Organizations

Contextual Info: SN74V215, SN74V225, SN74V235, SN74V245 512 x 18, 1024 × 18, 2048 × 18, 4096 × 18 DSP-SYNC FIRST-IN, FIRST-OUT MEMORIES SCAS636E – APRIL 2000 – REVISED SEPTEMBER 2002 D D D D D D D D D 512 × 18-Bit Organization Array SN74V215 1024 × 18-Bit Organization Array

Contextual Info: MN3300 Series MN3304 512-Stage Ultra Low Voltage Operation BBD for Audio Signals • Overview ■ Pin Assignment M Di ain sc te on na tin nc ue e/ d The MN3304 is a 512-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3V

ml86v8208

Abstract: ML86V8208 Application Notes PEUL86V8208OSD-01 ML86V8208 oki
Contextual Info: PEUL86V8208OSD-01 Preliminary ML86V8208 On-Screen Display OSD User’s Manual Issue Date: January 31, 2006 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date.

SN74V3640

Abstract: SN74V3640-6 SN74V3650 SN74V3650-6 SN74V3660 SN74V3660-6 SN74V3670 SN74V3680 SN74V3690
Contextual Info: SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 x 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 D D D D D D D D D Choice of Memory Organizations

MN3307

Abstract: BBD delay line MN3300 fcp 40
Contextual Info: MN3300 Series MN3307 1024-Stage Ultra Low Voltage Operation BBD for Audio Signals • Overview ■ Pin Assignment ■ Features ue pl d in an c se ed lud pl vi an m m es si tf ed ain ai fo ol t n l ht low disc dis ena ten low tp in o co n an in :// g nt n ce c g

7C235A-40

Abstract: CY7C235A CY7C235A-25PC CY7C235A-30JC CY7C235A-40DMB CY7C235A-40PC 7C235A-30
Contextual Info: 1CY7C235A CY7C235A 1K x 8 Registered PROM Features • Capable of withstanding greater than 2001V static discharge • CMOS for optimum speed/power • High speed — 25 ns address set-up Functional Description The CY7C235A is a high-performance 1024-word by 8-bit

Contextual Info: MN3300 Series MN3307 1024-Stage Ultra Low Voltage Operation BBD for Audio Signals • Overview ■ Pin Assignment M Di ain sc te on na tin nc ue e/ d The MN3307 is a 1024-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on

MN3300

Abstract: MN3306 rl56k BBD delay line fcp 40
Contextual Info: MN3300 Series MN3306 128-Stage Ultra Low Voltage Operation BBD for Audio Signals • Overview ■ Pin Assignment The MN3306 is a 128-stage ultra low voltage operation BBD variable delay line in audio frequency range. The device operates on +3V supply and provides a signal delay up to 6.4 ms and is suitable for

AC+121+V+TPI+121

Contextual Info: 2: 43 AM TUPP 2488 ASSP Telecom Standard Product Data Sheet Released ay ,1 8N ov em TUPP™ 2488 be r, 20 04 03 :5 PM5364 Data Sheet Released Issue No. 7: August 2004 Do wn l oa de d by C on te n tT ea m of Pa r tm in er In co n Th ur sd SONET/SDH Tributary Unit Payload

CY7C235A

Abstract: CY7C235A-25PC CY7C235A-30JC CY7C235A-40DMB CY7C235A-40PC 7C235A-40 C235A
Contextual Info: 1CY7C235A CY7C235A 1K x 8 Registered PROM Features • Capable of withstanding greater than 2001V static discharge • CMOS for optimum speed/power • High speed — 25 ns address set-up Functional Description The CY7C235A is a high-performance 1024-word by 8-bit

Contextual Info: SN74V3640, SN74V3650, SN74V3660, SN74V3670, SN74V3680, SN74V3690 1024 x 36, 2048 × 36, 4096 × 36, 8192 × 36, 16384 × 36, 32768 × 36 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS668A – NOVEMBER 2001 – REVISED MARCH 2003 D D D D D D D D D Choice of Memory Organizations

SN74V215

Abstract: SN74V225 SN74V235 SN74V245
Contextual Info: SN74V215, SN74V225, SN74V235, SN74V245 512 x 18, 1024 × 18, 2048 × 18, 4096 × 18 3.3-V CMOS FIRST-IN, FIRST-OUT MEMORIES SCAS636B – APRIL 2000 – REVISED SEPTEMBER 2000 D D D D D D D D D 512 × 18-Bit Organization Array SN74V215 1024 × 18-Bit Organization Array

Contextual Info: 2: 59 AM TUPP 2488 ASSP Telecom Standard Product Data Sheet Released ay ,1 8N ov em TUPP™ 2488 be r, 20 04 03 :5 PM5364 Data Sheet Released Issue No. 7: August 2004 Do wn l oa de d by C on te n tT ea m of Pa r tm in er In co n Th ur sd SONET/SDH Tributary Unit Payload