The Datasheet Archive

Top Results (6)

Part ECAD Model Manufacturer Description Datasheet Download Buy Part
70T3509MS133BP 70T3509MS133BP ECAD Model Renesas Electronics Corporation 1024K x 36 Sync, 3.3V/2.5V Dual-Port RAM
70T3509MS133BPI 70T3509MS133BPI ECAD Model Renesas Electronics Corporation 1024K x 36 Sync, 3.3V/2.5V Dual-Port RAM
70T3509MS133BPG 70T3509MS133BPG ECAD Model Renesas Electronics Corporation 1024K x 36 Sync, 3.3V/2.5V Dual-Port RAM
70T3509MS133BPGI 70T3509MS133BPGI ECAD Model Renesas Electronics Corporation 1024K x 36 Sync, 3.3V/2.5V Dual-Port RAM
AT25XE512C-XMHN-B AT25XE512C-XMHN-B ECAD Model Renesas Electronics Corporation 512Kbit, 1.65V to 3.6V Range SPI Serial Flash Memory with Dual Read Support and low Read Current
AT25XE512C-SSHN-B AT25XE512C-SSHN-B ECAD Model Renesas Electronics Corporation 512Kbit, 1.65V to 3.6V Range SPI Serial Flash Memory with Dual Read Support and low Read Current

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1996 - RBS4

Abstract: MPC860 MT4C16270 RBS200
Text: 0 0 RSS 0 0 0 0 0 0 0 0 RSS+1 0 0 1 0 0 1 1 1 RSS+2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13 Bit 14 Bit 15 Bit 16 Bit 17 Bit 18 Bit 19 Bit 20 Bit 21 Bit 22 Bit 23 Bit 24 Bit 25 Bit 26 Bit 27 Bit 28 Bit 29 Bit 30 Bit 31 Figure 15-35. Single Beat Read Access To Page Mode DRAM MOTOROLA MPC860 , +2 Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Bit 8 Bit 9 Bit 10 Bit 11 Bit 12 Bit 13


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PDF MPC860 RBS4 MT4C16270 RBS200
2014 - Not Available

Abstract: No abstract text available
Text: ! 8- bit micro Correlation ! Processor " ! ! Detector Bias ! Voltage ! Power User , " .1m/s" 0xC8" 40" .25m/s" 0x50" 20" .5m/s" 0x28" 10" 1m/s" 0x14" ! Velocity"is"output"as"an"8! bit , Control!Register!#75(0x4b)"(control_reg"[75]:)" Bit "7" Bit "6" Bit "5" Bit "4" Bit "3" Bit "2" " " , " Select"Range"Criteria" Select"Max"Range" Bit "1" Select"Range" Criteria" Bit "0" Select"Second" Return , )"–"Mode"Control"(control_reg[4]:)" Bit "7" Bit "6" Velocity"" Inhibit"Reference" Bit "5" Velocity"Scale


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PDF 639H8842' 100msec 10msec
1999 - MIL-HDBK-1553B

Abstract: VMIVME 6000 VMIVME-6000 mil-std-1553b SPECIFICATION BJ77 Trompeter Electronics Trompeter Electronics BJ 72 XFMR 5321 VMIC 6000 trompeter BJ77
Text: .4-190 Bit Failed .4-190 Bit Data Compare (Loop Fail , .4-194 Bit Count Error , .4-166 Bit Word , Release-on-Acknowledge (ROAK). The board will provide a 16- bit interrupt vector (programmable by the host) during the


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PDF VMIVME-6000 MIL-HDBK-1553B VMIVME 6000 VMIVME-6000 mil-std-1553b SPECIFICATION BJ77 Trompeter Electronics Trompeter Electronics BJ 72 XFMR 5321 VMIC 6000 trompeter BJ77
2004 - 68HC908MR24

Abstract: 68HC908MR32 AN1844 MR24
Text: Bit 1 not used Bit 1 is STOP enable Break module None Included FLASH mapping $A000­$FDFF $8000­$FDFF FLASH erased state Erased bit = 0 Erased bit = 1 FLASH page size (bytes , registers reside in different addresses. For example, on the MR24, an erased FLASH bit reads as a logic 0 and a programmed bit reads as a logic 1. On the MR32, an erased FLASH bit reads as a logic 1 and a programmed bit reads as a logic 0. The MR32 will enter monitor mode when the reset vector ($FFFE­$FFFF) is


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PDF AN1844/D AN1844 68HC908MR32 68HC908MR24 68HC908MR32 68HC908MR24 AN1844 MR24
2000 - 68HC908MR32

Abstract: 68HC908MR24 AN1844 MR24
Text: Differences Function 68HC908MR24 68HC908MR32 CONFIG register Bit 1 not used Bit 1 is STOP , state Erased bit = 0 Erased bit = 1 FLASH page size (bytes) 8 128 FLASH minimum erase , addresses. For example, on the MR24, an erased FLASH bit reads as a logic 0 and a programmed bit reads as a logic 1. On the MR32, an erased FLASH bit reads as a logic 1 and a programmed bit reads as a , in the CPU (central processor unit) and bit 1 of the mask option register (MOR) was not used. The


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PDF AN1844/D AN1844 68HC908MR32 68HC908MR24 68HC908MR32 68HC908MR24 AN1844 MR24
MV1822

Abstract: No abstract text available
Text: six, data bit two being set high and bits 3 and 4 set low. Bytes 13 to 25 inclusive are Hamming , data consists of 15 eight bit words encoded in Manchester bi-phase format with a data rate of 2 â , packet 8/30 format one is received, the UDT data in 8 bit format, starting with byte 13, is read into the , set high, or 0010 0011 (22+1 hex) with the AS pin set low. The read bit (LSB) must always be set, it , acknowledge and then transmit on the SDA line the first byte from the output registers, most significant bit


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PDF MV1822 HB3120 MV1822, 2-65s 160ms
1999 - spi eeprom flash programmer schematic

Abstract: 3 phase MOTOR CONTROL ic 2X16 lcd PIN OUT LCD 1X16 40X4 LCD LCD 2x16-Bit ST6201C ST6220C ST6225C microcontroller ST7 tutorial
Text: BIT Family ST7MDT4-EMU2 ST7263-EMU2 ST90158-EMU2 ST92F120-EMU2 ST92141-EMU2 NOHAU None , ST7MDT1-DBE ST7MDT2-EMU2 /XXX TEMPERATURE RANGE (or SPEED, 32- Bit Families) ST628X-DBE , chlorine free paper Device EMULATORS MICROCONTROLLER PRODUCT FINDER STMicroelectronics 8 & 16- BIT , ST72124J24) ST72124J44) ST72213G1 q q q q q q q q q ST72216G14) q 8- BIT ST6 ST6200C , ST6240B ST6242B ST6246B ST6252C ST6253C ST6255C ST6260C ST6262C ST6263C ST6265C 8/16- BIT ST9


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PDF ST62E2XC-EPB1) ST62E3X-EPB1) ST62E4XB-EPB1) ST62E6XB-EPB1) ST62E8X-EPB1) ST62E0X-GP/DIP ST62E0X-GP/SO ST62E10-GP/DIP ST62E10-GP/SO ST62E15-GP/DIP spi eeprom flash programmer schematic 3 phase MOTOR CONTROL ic 2X16 lcd PIN OUT LCD 1X16 40X4 LCD LCD 2x16-Bit ST6201C ST6220C ST6225C microcontroller ST7 tutorial
UT80CRH196KD

Abstract: No abstract text available
Text: UT80CRH196KD will detect both single and double bit errors, and correct single bit errors in the data , data. Further, you will learn how the UT80CRH196KD reacts to single, double, and triple bit errors , information word. Each check bit represents the parity of a specific subset of data bits. The check bit generation scheme for encoding data is described by the matrix in Table 1. Every check bit is created by , P- and N-channel MOSFETS for the respective inputs. TABLE 1. Check Bit Generation 16 Bit Data


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PDF UT80CRH196KD
1997 - CD4046 vco

Abstract: LM324 temperature controller MM74HC123 cd4046
Text: Note 1) SERIAL DATA 22 35- BIT SHIFT REGISTERS LOAD RESET CLOCK 21 1 Note 1: Pin 23 is Data Enable , 8-26 December 1997 MM5450/5451 OUTPUT BIT 13 OUTPUT BIT 14 OUTPUT BIT 15 OUTPUT BIT 16 OUTPUT BIT 17 OUTPUT BIT 18 OUTPUT BIT 19 OUTPUT BIT 20 OUTPUT BIT 21 OUTPUT BIT 22 OUTPUT BIT 23 Micrel Connection Diagram: Die OUTPUT BIT 12 OUTPUT BIT 11 OUTPUT BIT 10 OUTPUT BIT 9 OUTPUT BIT 8 OUTPUT BIT 7 V SS OUTPUT BIT 6 OUTPUT BIT 5 OUTPUT BIT 4 OUTPUT BIT 3 MM5450/5451 DIE PINOUT V SS OUTPUT BIT


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PDF MM5450/5451 MM5450 MM5451 MM5450) LM324 2N2907 CD4046 MM5450 MM74HC123 CD4046 vco LM324 temperature controller cd4046
EM78P154N

Abstract: EM78P157N EM78P159N otp rom EM78P154NP
Text: Product Specification (V1.0) 03.10.2006 EM78P154N 8- Bit Microcontroller with OTP ROM 1 General , .0) 03.10.2006 (This specification is subject to change without further notice) 1 EM78P154N 8- Bit , is subject to change without further notice) EM78P154N 8- Bit Microcontroller with OTP ROM 3 , 8- Bit Microcontrollerwith OTP ROM 4 Function Description OSCO /RESET OSCI TCC WDT timer , 8- Bit Microcontroller with OTP ROM 4.1.3 R2 (Program Counter) & Stack On-chip Program Memory


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PDF EM78P154N EM78P154N EM78P157N EM78P159N otp rom EM78P154NP
Not Available

Abstract: No abstract text available
Text: -CAE4C5E1 A7C61C967C51 HSYNC signal: HSYNC_LEVEL=SYNC TIP + HSYNCTH Address= 8’h00 VD Control 7- bit 6- bit 5- bit 4- bit 3- bit 2- bit 1- bit 0- bit 0 0 0 0 1 0 1 0 , Video decoding function S_Video: When input signal is S-Video, set this bit to be 1 BBRSTZ: Base Band , NTSC/PAL Decoder1 1 Address= 8’h01 WATCHSEL 7- bit 6- bit 5- bit 4- bit 3- bit 0 0 3- bit 2- bit 1 4’hf 2- bit 0 1- bit 0- bit 2’b01 AGC_LMT AGC_LMT: Analog


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PDF DM5150 DM5150-DS-P01
2002 - MB89135L

Abstract: MB89P637 MB89P131 MB89P133A FR30 MB89121 MB89123A MB89125A MB89131 MB89133A
Text: Entire Site Site map Support Microcontrollers F2MC 8 Bit Series 16 Bit Series FR 32- Bit , 3 4 128 (32) 8 Power- Pin Saving Count Modes 2 x 8 bit 11 or 11 1 x 16 bit 3 2 X 8 bit 3 or on-chip STOP 256 11 1 x 16 bit Remote , 16 bit 12 bit CLOCK MB89146 130/A 3 MB89144 120/A 24 768 Programmable , Features 36 1x8 bit 1x8 bit Yes 4x8 bit (A-Version with SLEEP on-chip STOP


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PDF 32-Bit MB89xxx MB89121 MB89123A MB89125A MB89131 MB89P131 MB89P985 MB89997 MB90Pxxx MB89135L MB89P637 MB89P131 MB89P133A FR30 MB89121 MB89123A MB89125A MB89131 MB89133A
C3641

Abstract: No abstract text available
Text: AE4C5E1 A7C61C967C51 HSYNC signal: HSYNC_LEVEL=SYNC TIP + HSYNCTH Address= 8’h00 VD Control 7- bit 6- bit 5- bit 4- bit 3- bit 2- bit 1- bit 0- bit 0 0 0 0 1 0 1 0 , Video decoding function S_Video: When input signal is S-Video, set this bit to be 1 BBRSTZ: Base Band , channel NTSC/PAL Decoder 1 Address= 8’h01 WATCHSEL 7- bit 6- bit 5- bit 4- bit 3- bit 0 0 3- bit 2- bit 1 4’hf 2- bit 0 1- bit 0- bit 2’b01 AGC_LMT AGC_LMT


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PDF DM5160 DM5160-DS-P01 C3641
1998 - hc08as60

Abstract: 68HC08AS60 hc08 4 bit 4 bit parity generator M68HC08AS60
Text: corresponding port e.g. "PortAVal". For each "PortXVal" register, it exists for each available bit a separate , bit number e.g. "PortABit0". If a "PortXBitY" register is set to zero, it means that the correspending bit of the "PortXVal" register is cleared, otherwise it is set. Registers: PTA, PTB, PTC, PTD , register for port X PortXBitY Not memory mapped register for bit Y of port X Clock Generator Module , be generated. bit 7 PLLIE bit 6 PLLF bit 5 PLLON bit 4 BCS bit 3.0 PLL Interrupt Enable Bit


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PDF 68HC08AS60 M68HC08AS60 M68HC08AS60 HC08AS60 hc08as60 68HC08AS60 hc08 4 bit 4 bit parity generator
Not Available

Abstract: No abstract text available
Text: bit two being set high and bits 3 and 4 set low. Bytes 13 to 25 inclusive are Hamming decoded (8,4 , consists of 15 eight bit words encoded in Manchester bl-phase format with a data rate of 2 • 5Mbits/sec , data in 8 bit format, starting with byte 13, is read into the internal registers provided the l2C bus , the address select (AS) pin set high, or 0010 0011 (22+1 hex) with the AS pin set low. The read bit , registers, most significant bit (MSB) first. It will then monitor the SDA line “for an acknowledgeâ


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PDF MV1822 MV1822 002534b MV1822, 625x64 isx64 160ms G025347
SN8F2288F

Abstract: SN8F2288 SN8F2288FG SN8F2288J SN8F2283J T1C10 Vreg25 urx 134 SN8F2283 74h 132
Text: SN8F2280 Series USB 2.0 Full-Speed 8- Bit Micro-Controller SN8F2280 SN8F2288 SN8F2283 , ., LTD Page 1 Version 1.4 SN8F2280 Series USB 2.0 Full-Speed 8- Bit Micro-Controller VER , TECHNOLOGY CO., LTD Page 2 Version 1.4 SN8F2280 Series USB 2.0 Full-Speed 8- Bit Micro-Controller , .42 SONiX TECHNOLOGY CO., LTD Page 3 Version 1.4 SN8F2280 Series USB 2.0 Full-Speed 8- Bit , .86 SONiX TECHNOLOGY CO., LTD Page 4 Version 1.4 SN8F2280 Series USB 2.0 Full-Speed 8- Bit


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PDF SN8F2280 SN8F2280 SN8F2288 SN8F2283 QFN48 SN8F2288F SN8F2288 SN8F2288FG SN8F2288J SN8F2283J T1C10 Vreg25 urx 134 SN8F2283 74h 132
MDT10F676

Abstract: mdt10f676p11 MDT10F676S11 MDT10F676S13 5F60 DSA006234 remote control toy 2007 4Mhz oscillator
Text: range This 8- bit Micro-controller uses a fully static from appliance motor control and high speed , , chargers, and toy, MDT10F676P11 (DIP) 8- bit data bus MDT10F676S11 (SOP) On chip flash ROM , PA0/CIN+ PA1/CINPA2/INT PC0 PC1 PC2 37 single word instructions 14- bit instructions 8 , PC4 PC3 8 analog input multiplexed into one A/D converter with 10- bit resolution Timer0 : 8- bit timer with 3- bit prescaler Timer1 : 16- bit timer with 2- bit prescaler One analog comparator module


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PDF MDT10F676 MDT10F676 MDT10F676P11 MDT10F676S11 mdt10f676p11 MDT10F676S11 MDT10F676S13 5F60 DSA006234 remote control toy 2007 4Mhz oscillator
motorola 6526

Abstract: No abstract text available
Text: Revision Code Default Value: x'OD Access: Byte Read/Write Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 , : Channel Access Default Value: x'03 Access: Byte Read/Write Bit 7 B it6 | Bit 5 Reserved Bit 4 Advanced , Bit 3 Bit 2 Bit 1 C1 BitO CO This register contains the channel number for the , : CMR Register Description: Channel Mode Default Value: x'02 Access: Byte Read/Write Bit 7 RxMode Bit 6 TxMode Bit 5 0 Bit 4 0 Bit 3 0 Bit 2 chmd2 Bit 1 chmdl BitO chmdO Bit 7 Receive Transfer mode


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PDF CL-CD2431 CL-CD2431. CL-CD2431 motorola 6526
1996 - hecs 50

Abstract: atm header error checking BIP 109 atm header-error-check multiple bit BIP-8 cmos 4 bit counter STM-1 Physical interface PHY TCA 810 128-PIN GR-253-CORE
Text: Multi-PHY connections with 2bit address and 8- bit data using UTOPIA 2 protocol. · Provides an 8- bit , recovered from RXD+/- bit stream. RBYP has an integral pull down resistor. Pin #: 41 RCA/ TXEMPTY , enable the insertion of each bit . By default, the GFC values contain the header information of the , . This unit provides a status bit to indicate whether it is locked to data or the reference clock. The , clock if there is no data transition for an 80 bit period or the recovered clock drifts for over 244


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PDF IDT77155 84Mbps GR-253-CORE hecs 50 atm header error checking BIP 109 atm header-error-check multiple bit BIP-8 cmos 4 bit counter STM-1 Physical interface PHY TCA 810 128-PIN
PCMCIA 2.1

Abstract: No abstract text available
Text: Control 1 Index: 16h Bit 7 Inpack Enable RW:0 CL-PD6729 rCIRRUS LOGIC Register Per: socket Register Compatibility Type: ext. Bit 5 Bit 4 Speaker Enable RW:0 Bit 6 I Bit 3 Pulse System IRQ RW:0 Bit 2 Pulse Management Interrupt RW:0 Bit 1 Vcc 3.3V RW:0 BitO Multimedia Enable RW:0 Scratchpad Bits RW:00 Bit 0: Multimedia Enable 0 1 Socket address lines are normal. Socket address lines A[25:4] are high-impedance. This bit tristates socket address lines A[25:4]. All other


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PDF CL-PD6729 CL-PD6729 PCMCIA 2.1
SYM53C720

Abstract: SYM53C710 intel 80386dx intel 80386sx SYM53C-720
Text: . Preview of Next Address 14. Carry Bit In ALU 15. Semaphore Bit 16. Devices on SCSI Bus 17. Host Parity , INTFLY Instruction Function The INTFLY instruction (DBC, bit 20) will assert the Interrupt on the Fly bit (ISTAT, bit 2) once the SCRIPTS instruction is executed. SCRIPTS programs will not halt when the , Jump, Call, Return or Interrupt may be executed depending on the resulting carry bit (DBC, bit 21 , Function When carry is enabled (DCMD, bit 0) any read/write opcode utilizing the add operation will also


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PDF SYM53C710 SYM53C720 SYM53C710. SYM53C710 32-bit E05973I 0597-15MX intel 80386dx intel 80386sx SYM53C-720
2004 - crystal oscillator clock 3.579MHZ

Abstract: ph77 622 7 segment ph73 P8276 EM78862 EM78862B EM78869 EM78P862A PH-77
Text: EM78862B 8- Bit RISC Type Microprocessor Product Specification DOC. VERSION 1.2 ELAN , .2) 09.19.2007 EM78862B 8- Bit RISC Type Microprocessor 1 General Description The EM78862B is an 8- bit , series. Item EM78862 EM78862B EM78869 ROM size 16K X 13 bit 8K X 13 bit RAM size 2.2K X 8 bit 2.2K X 8 bit 0.7K X 8 bit LCD 60 X 9 60 X 9 40 X 9 LCD RAM Write , 2 16K X 13 bit EM78P862A EM78P862A EM78P862A Features 2.1 CPU Operating voltage


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PDF EM78862B crystal oscillator clock 3.579MHZ ph77 622 7 segment ph73 P8276 EM78862 EM78862B EM78869 EM78P862A PH-77
2008 - Not Available

Abstract: No abstract text available
Text: / LAPS/ HDLC 8- BIT & SPI μP INTERFACE BUFFER MANAGER SDRAM CONTROLLER QoS POLICY MACs , . 104 10.1 REGISTER BIT MAPS .105 10.1.1 10.1.2 10.2 Global Register Bit Map . 105 MAC Indirect Register Bit Map , .188 10.4.1 10.5 10.6 10.7 Arbiter Register Bit Descriptions


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PDF DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 DS33X162 10/100/1000Mbps 52Mbps 35/Optical. DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
2003 - ph76

Abstract: ph77 EM78862 EM78862B EM78869 EM78P862A ph71
Text: EM78862B 8- Bit RISC Type Microprocessor Product Specification VERSION 1.1 ELAN , . 35 iv EM78862B Specification EM78862B 8- Bit RISC Type Microprocessor 1 General Description The EM78862B is an 8- bit RISC type microprocessor with low power, high speed CMOS technology , other MCU's of the same series. Item EM78862 EM78862B EM78869 ROM size 16K X 13 bit 8K X 13 bit RAM size 2.2K X 8 bit 2.2K X 8 bit 0.7K X 8 bit LCD 60 X 9 60 X 9


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PDF EM78862B Mar-01-2005 ph76 ph77 EM78862 EM78862B EM78869 EM78P862A ph71
Not Available

Abstract: No abstract text available
Text: channels support async-HDLC/PPP, async, HDLC, or programmable sync ■Sync bit rates up to 8 Mbits/sec , to 256 kbps ■All four channels completely independent for protocol and bit rate selection â , . Each channel can operate at bit rates up to 8 Mbits/sec. (up to 52 Mbits/sec. data rate on a single , independent for protocol and bit-rate selection ■Sync bit rates up to 8 Mbits/sec. on all channels â , ARM7 CPU HW hardware ISA industry standard architecture LSB least-significant bit


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PDF CL-CD4400
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