1.9 TDI Search Results

Contextual Info: January 2008 HYS[64/72]T64000EU–[1.9/19F]–C HYS[64/72]T128020EU–[1.9/19F]–C 2 4 0 - P i n u n b u f f e r e d D D R 2 S D R A M Mo d u l e s UDIMM SDRAM RoHS Compliant Internet Data Sheet Rev. 1.0 Internet Data Sheet HYS[64/72]T[64/128]0x0EU–[1.9/19F]–C

pc2-6400u-666-12-d0

Abstract: HYS64T256020EU-19F-C2 pc2-6400u-666-12-e0 HYS72T256020EU-2 HYS64T128000EU PC2-6400E-666-12-F0 HYS72T256020EU HYS72T128000EU PC2-6400E-666-12-G0 HYS64T256
Contextual Info: June 2008 HYS64T128000EU–[19F/1.9/25F/2.5/3S]–C2 HYS72T128000EU–[25F/2.5/3S]–C2 HYS64T256020EU–[19F/1.9/25F/2.5/3S]–C2 HYS72T256020EU–[25F/2.5/3S]–C2 240-Pin Unbuffered DDR2 SDRAM Modules UDIMM SDRAM EU RoHS Compliant Internet Data Sheet Rev. 1.00

MX25L1605D

Abstract: MX25L1635D IN3064
Contextual Info: MX25L1635D MX25L1635D DATASHEET P/N: PM1374 1 REV. 1.9, SEP. 08, 2009 MX25L1635D Contents FEATURES. 5

Contextual Info: MX25U1635E MX25U1635E DATASHEET P/N: PM1472 1 REV. 1.9, NOV. 08, 2013 MX25U1635E Contents 1. FEATURES. 6

Contextual Info: MX25U3235E MX25U3235E DATASHEET P/N: PM1472 1 REV. 1.9, NOV. 11, 2013 MX25U3235E Contents 1. FEATURES. 6

Contextual Info: MX25L6436E MX25L6436E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1772 1 REV. 1.9, APR. 30, 2012 MX25L6436E Contents FEATURES. 5

Serial Flash

Contextual Info: MX25L12845E MX25L12845E HIGH PERFORMANCE SERIAL FLASH SPECIFICATION P/N: PM1428 REV. 1.9, SEP. 06, 2013 1 MX25L12845E Contents FEATURES. 5

K643

Abstract: 65A3 n373 276C 238e ts-w 307f K573 2732 memory chip motorola 5118 user manual ber 2a37 rX 433 N
Contextual Info: S19204CBI12 MEKONG Datasheet Rev 1.9 September 16, 2002 AMCC - PROPRIETARY AND CONFIDENTIAL RESTRICTED DISTRIBUTION NDA REQUIRED AMCC - Confidential and Proprietary Dear customer, Thank you for choosing an AMCC device. We appreciate your confidence in our products.

TTL to LVTTL level shifter

Contextual Info: a Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎ 100 mV 1.9 GHz Minimum Bandwidth

ADN2811

Abstract: STM-16
Contextual Info: OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp ADN2811 FEATURES PRODUCT DESCRIPTION Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth

Contextual Info: Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES PRODUCT DESCRIPTION Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth

Contextual Info: OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp ADN2811 FEATURES PRODUCT DESCRIPTION Meets SONET requirements for jitter transfer/generation/ tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth

ADN2819

Abstract: OC-24
Contextual Info: Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES PRODUCT DESCRIPTION Meets SONET requirements for jitter transfer/generation/tolerance Quantizer sensitivity: 4 mV typical Adjustable slice level: ±100 mV 1.9 GHz minimum bandwidth

Contextual Info: DRV8811 www.ti.com SLVS865H – SEPTEMBER 2008 – REVISED NOVEMBER 2013 STEPPER MOTOR CONTROLLER IC Check for Samples: DRV8811 FEATURES 1 • Pulse Width Modulation PWM Microstepping Motor Driver – Built-In Microstepping Indexer – Up to 1.9-A Current Per Winding

c0301

Abstract: ADN2811 ADN2811ACP-CML ADN2811ACP-CML-RL CP-48 GR-253-CORE STM-16 Fiber Optic regenerator 28
Contextual Info: a OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp ADN2811 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎100 mV 1.9 GHz Minimum Bandwidth Patented Clock Recovery Architecture

106 25K

Abstract: 6608 6 channels rc receiver double diode 5341 2312 2551 5602
Contextual Info: 1. Stratix III Device Datasheet: DC and Switching Characteristics SIII52001-1.9 Electrical Characteristics Operating Conditions When Stratix III devices are implemented in a system, they are rated according to a set of defined parameters. To maintain the highest possible performance and

vhdl code for 1 bit error generator

Contextual Info: Cyclone IV Device Handbook, Volume 1 Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.9 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

Contextual Info: Cyclone IV Device Handbook, Volume 1 Cyclone IV Device Handbook, Volume 1 101 Innovation Drive San Jose, CA 95134 www.altera.com CYIV-5V1-1.9 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

h10s raltron

Abstract: ADN2819 ADN2819ACP-CML ADN2819ACP-CML-RL CP-48 GR-253-CORE OC-24 H10S-19
Contextual Info: a Multirate to 2.7 Gb/s Clock and Data Recovery IC with Integrated Limiting Amp ADN2819 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎100 mV 1.9 GHz Minimum Bandwidth Patented Clock Recovery Architecture

Contextual Info: a OC-48/OC-48 FEC Clock and Data Recovery IC with Integrated Limiting Amp ADN2811 FEATURES Meets SONET Requirements for Jitter Transfer/ Generation/Tolerance Quantizer Sensitivity: 4 mV Typ Adjustable Slice Level: ؎100 mV 1.9 GHz Minimum Bandwidth Patented Clock Recovery Architecture

Ethernetblaster

Abstract: pin configuration of buffer EP3SE50 EPCS128 EPCS16 EPCS64
Contextual Info: 11. Configuring Stratix III Devices SIII51011-1.9 This chapter contains complete information about Stratix III supported configuration schemes, how to execute the required configuration schemes, and all necessary option pin settings. Stratix III devices use SRAM cells to store configuration data. Because SRAM memory

A42 BF 331

Abstract: Date Code Formats diodes St Microelectronics MCF5272C3 JP13 M5272C3 M5407C3 MCF5272 LST670 equivalent MOLEX RJ45 lxt971l
Contextual Info: M5272C3 User’s Manual M5272C3UM/D Rev. 1.2, 1/2001 CONTENTS Paragraph Number Title Page Number Chapter 1 M5272C3 Board 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 1.9 1.9.1 1.9.2 1.9.3 1.9.4 1.9.5 1.9.6 1.9.7 1.10 1.11 1.12 General Hardware Description . 1-1

Contextual Info: CDCUA877 www.ti.com SCAS769A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER • FEATURES • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate DDR II Applications Spread Spectrum Clock Compatible

Contextual Info: CDCUA877 www.ti.com SCAS769A – AUGUST 2006 – REVISED JUNE 2007 1.8-V PHASE LOCK LOOP CLOCK DRIVER • FEATURES • • • • • • • • 1.8-V/1.9-V Phase Lock Loop Clock Driver for Double Data Rate DDR II Applications Spread Spectrum Clock Compatible