1-BIT D LATCH Search Results

dimm pcb layout

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

D8-D25

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER D14-D25
Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

A115-A

Abstract: C101 SN74SSTU32864 SN74SSTU32864GKER
Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

Contextual Info: SN74SSTU32864 25-BIT CONFIGURABLE REGISTERED BUFFER WITH SSTL_18 INPUTS AND OUTPUTS SCES434 – MARCH 2003 D D D D D D D Member of the Texas Instruments Widebus+ Family Pinout Optimizes DDR-II DIMM PCB Layout Configurable as 25-Bit 1:1 or 14-Bit 1:2 Registered Buffer

TMS664164

Abstract: TMS664414 TMS664814
Contextual Info: TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 D D D D D D D D D D D D Organization . . . 1 048 576 x 16 Bits x 4 Banks

TMS664164

Abstract: TMS664414 TMS664814
Contextual Info: TMS664414, TMS664814, TMS664164 4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS695A – APRIL 1998 – REVISED JULY 1998 D D D D D D D D D D D D Organization . . . 1 048 576 x 16 Bits x 4 Banks

ADS1202

Abstract: ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 QFN32 5x5 package a4350
Contextual Info: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs

Contextual Info: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs

ADS1202

Abstract: ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32
Contextual Info: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs

Contextual Info: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs

Contextual Info: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs

QFN32 5x5 package

Abstract: ADS1202 ADS1204 ADS1204IRHBR ADS1204IRHBT QFN-32 a4350
Contextual Info: ADS1204 SBAS301A − OCTOBER 2003 − REVISED JUNE 2004 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal Delay 12-Bit with 19µs

Contextual Info: IR3K01 8-Bit A /D Converter / IR3K01 • 8-Bit A/D Converter Pin Connections Description T he IR3K01 is a monolithic 8-bit A/D converter featuring an internal timer, V/F converter, counter and latch. f B IT 1 M S B ' D a ta ■ 1. 2. 3. 4. 5. 6. 7. 8. S ta r t

Contextual Info: S M A « * ? H I 1 1 7 2 , C X D 1 1 7 2 6-Bit 20 MSPS Video A/D Converter CMOS February 1996 Features Description • R esolution. 6-Bit ± 1/2 LSB HI1172, CXD1172 is a 6-bit CMOS A/D converter for video

SMJ4C1024

Abstract: 4c1024 SMJ44C256 4C1024-15 4c10248
Contextual Info: SMJ4C1024 1048576 BY 1-BIT DYNAMIC RANDOM-ACCESS MEMORY SGMS023E – DECEMBER 1988 – REVISED MARCH 1996 D D D D D D D D D D D D D Organization . . . 1 048 576 x 1-Bit Processed to MIL-STD-883, Class B Single 5-V Supply 10% Tolerance Performance Ranges:

Contextual Info: D S 0 4 -1 3 2 0 1 -3 a E : DATASHEET : LINEAR 1C CMOS 8 BIT 4-CHANNEL MB86022 D/A CONVERTER CMOS 8-BIT 4-CHANNEL D/A CONVERTER The Fujitsu MB86022 is a 8-bit 4-channel Digital to Analog Converter which is fabricated with Fujitsu CMOS Technology. The data latch and output buffer circuitry

QFN32 5x5 package

Abstract: opa 2064
Contextual Info: ADS1204 SBAS301B − OCTOBER 2003 − REVISED AUGUST 2007 Four 1ĆBit, 10MHz, 2ndĆOrder, DeltaĆSigma Modulators FEATURES D 16-Bit Resolution D 14-Bit Linearity D Resolution/Speed Trade-Off: D D D D D D D D D 10-Bit Effective Resolution with 10µs Signal