1 K OHM Search Results

5K potentiometer multiturn

Abstract: 20K3 potentiometer 10-turn 5k
Contextual Info: PART REV. SPECIFICATIONS D ELECTRICAL RESISTANCE VALUES NO. BY DATE 03-05 BT 00 MH22B OUTPUT SMOOTHNESS WAS .15 1 K ,2 K ,5 K ,1 0 K ,2 0 K ,5 0 K ,1 0 0 K OHM S 10 TURN 500,1 K ,2 K ,5 K ,1 0 K ,2 0 K ,(3 AND 5 TURNS) ± 10% RESISTANCE TOLERANCE INDEPENDENT LINEARITY

s8 223j

Abstract: s6 5n 822j MS75089 MS75089-23 MS75088-13 S75087
Contextual Info: OHMITE LITTLE HENRIES" Inductive Components K Series Manufacturing Company R. F. Molded Chokes 1 4 3 8 ! 188 -3 6 525-± 4 7 7- 156 - 0 1 0 - 3 . 9 6 2 a- 25 '0 K M 150M K M 220M K M 330M K M 470M KM 5 60 K 18130-1 18130-2 18130-3 18130-4 18130-5 KM 680K KM 820K

stk 4141 circuit

Abstract: STK4141II STK4191II STK 4141 2 STK 4171 II STK4121II STK4171II stk power amp STK4151II 4101II
Contextual Info: STK4101 H SERIES Applications • S T K 4 1 0 1 II: ■ S T K 4 1 1111: ■ S T K 4 1 2 1 II: ■ S T K 4 1 3 1 II: ■ S T K 4 1 4 1 II: t ï h 6W min 10W min 15W min 20W min 25W min AF AF AF AF AF i Ô k , ' f ;I l r r > fC ;2 . S T K 4 1 5 1 II: S T K 4 1 6 1 II:

IDT722X1

Abstract: CY7C4241
Contextual Info: CY7C4221 CY7C42311 K / 2 K x 9 Synchronous FIFOs CY7C4221 / CY7C4231 1 K / 2 K × 9 Synchronous FIFOs 1 K / 2 K × 9 Synchronous FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories ❐ 1 K × 9 (CY7C4221) ❐ 2 K × 9 (CY7C4231)

Contextual Info: CY7C4221 CY7C42311 K / 2 K x 9 Synchronous FIFOs CY7C4221 / CY7C4231 1 K / 2 K × 9 Synchronous FIFOs 1 K / 2 K × 9 Synchronous FIFOs Features Functional Description • High-speed, low-power, first-in first-out FIFO memories ❐ 1 K × 9 (CY7C4221) ❐ 2 K × 9 (CY7C4231)

CY7C136E-55NXC

Abstract: CY7C131E-55 cy7c136e CY7C131E-15NXI CY7C136AE-55NXI
Contextual Info: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

CY7C136E

Abstract: CY7C131AE-15JXI CY7C136AE-55NXI
Contextual Info: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

CY7C136E

Contextual Info: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

CY7C136E

Contextual Info: CY7C131E, CY7C131AE CY7C136E, CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Functional Description Features • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

CY7C136E

Contextual Info: CY7C131E/CY7C131AE CY7C136E/CY7C136AE 1 K / 2 K x 8 Dual-port Static RAM 1 K / 2 K × 8 Dual-port Static RAM Features Functional Description • True dual-ported memory cells, which allow simultaneous reads of the same memory location ■ 1 K / 2 K × 8 organization

6250G

Abstract: CF160 CF160* Bosch TLE 6250G bosch cf150 bosch ic E928 6250 Bosch bosch k line
Contextual Info: TLE 6250 G EMC - Results: DPI HS- Mode/ Slope- Control R11 1,3 kΩ R13 1,3 k Ω DR1 R15 1 kΩ CAN-HSTC 1 CANL RX RX1 TX TX1 Test System: CANH R12 1,3 kΩ R14 1,3 k Ω 3 Transceivers on 1 PCB with R16 1 kΩ GND Vcc C13 4,7 nF max. external circuitry C11

KFU8-UFC-1.D

Abstract: k-adp1 namur NE 43 VDE 0106 VDE 0106 Part 1 KFD2-UFC KFU8-UFC-1 namur standard ufc 101 kfd2
Contextual Info: Logic Control Units, Universal Frequency Converters KFU8-UFC-1* 1+ 10 k 3- 1+ 3400 Ω ≤ R ≤ 2 kΩ 1 K-ADP1 RS 232 3- 2 1+ 10 k 3- 1+ 3 + 2- 3 PC Signal processor TTL yellow/ red green U yellow TXD • • 1+ yellow yellow GND • • • 1-channel

AEE19-3460

Abstract: CH-502A
Contextual Info: RoHS AEE19-3460 High Frequency Transformer ELECTRICAL SPECIFICATIONS: 1. INDUCTANCE: 1KHz/0.1V HP-4284A 1 - 3: 10.0 K OHM ± 20% 6 - 4: 10 K OHM (LOAD) 2. DCR: (AT 25ºc CH-502A) 1 - 3: 820 OHM ±20% 6 - 4: 1.08 K OHM ±20% 3. HI-POT TEST: PRI TO SEC : AC 1000V 1mA FOR 1 SEC

AN1064

Abstract: an4359 circuit diagram for automatic voltage regulator G PLC connection CY14B101KA
Contextual Info: CY14B101KA CY14B101MA 1-Mbit 128 K x 8/64 K × 16 nvSRAM with Real Time Clock 1-Mbit (128 K × 8/64 K × 16) nvSRAM with Real Time Clock Features 1-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25 ns and 45 ns access times ❐ Internally organized as 128 K × 8 (CY14B101KA) or

KE214

Abstract: k-303p k30t K-30-T K303M
Contextual Info: RG-58/U, PRO-FLEX and PRO-FLEX PLUS Coaxial Cable Assemblies 1 r hL'lh Mudi 1 1Ì I !1 I K-301M K-301P I'i {HII H 1 PRO-FLEX cable, one N male, one mini-UHF male 1 1 K-301N M III PRO-FLEX cable, two N males PRO-FLEX cable, one N male, one UHF male K-301T

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

CY7C09099V

Contextual Info: CY7C09079V/89V/99V CY7C09179V/89V/99V CY7C09089V/99V CY7C09179V/99V 3.3 V 32 K/64 K/128 K x 8/9 Synchronous Dual-Port Static RAM 3.3 V 32 K/64 K/128 K × 8/9 Synchronous Dual-Port Static RAM Features • High speed clock to data access 6.5[1]/7.5[1]/9/12 ns max.

Contextual Info: 1.38 REF. NOTES: 1. FOR USE WITH M l7 / 1 1 9 —RG174, M 17/094-RG179 k M l7 / 1 13-RG316 CABLES. 2. FOR CABLING INSTRUCTIONS SEE C P -4 70 . 3. FOR CABLE TRIMMING USE KTD-165 k K T J -1 10. 4. FOR CRIMPING USE DIE K TH -2011. 5. INTERFACE PER MIL-STD-348. FIG. 3 0 1-2 AS APPLICABLE .

CY14a101

Contextual Info: CY14V101LA CY14V101NA 1-Mbit 128 K x 8/64 K × 16 nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Features Functional Description • 25 ns and 45 ns access times ■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16 (CY14V101NA) ■ Hands off automatic STORE on power down with only a small

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Contextual Info: CY14V101LA CY14V101NA 1-Mbit 128 K x 8/64 K × 16 nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Functional Description Features • 25 ns and 45 ns access times ■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16 (CY14V101NA) ■ Hands off automatic STORE on power down with only a small

CY14A

Abstract: CY14A101L
Contextual Info: CY14V101LA CY14V101NA 1-Mbit 128 K x 8/64 K × 16 nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Features Functional Description • 25 ns and 45 ns access times ■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16 (CY14V101NA) ■ Hands off automatic STORE on power down with only a small

Contextual Info: CY14V101LA CY14V101NA 1-Mbit 128 K x 8/64 K × 16 nvSRAM 1-Mbit (128 K × 8/64 K × 16) nvSRAM Features Functional Description • 25 ns and 45 ns access times ■ Internally organized as 128 K × 8 (CY14V101LA) or 64 K × 16 (CY14V101NA) ■ Hands off automatic STORE on power down with only a small