0021B30 Search Results

Contextual Info: SHARP Ver.1.1 9 6 /1 1 /2 2 - Limited usage of LH28F800SUD (In the case of 8bit configuration ) Programmingproblem at command and data We observed some operation error when you write commandand data in following timing. * Same timing of BEX# High and WE# High

bu2114

Contextual Info: Standard ICs 8-bit shift register and latch driver B U 2 1 1 4 /B U 2 1 1 4 F The BU2114 and BU2114F are CMOS ICs with low power consum ption, and are equipped with an 8-bit shift register latch. Data in the shift register can be latched asynchronously. The ou tputs 01 to 0 8 are open drain ou tputs (be­

Contextual Info: b lE ]> • 44clbECI3 OOPlbSO SbT ■ H I T S HM62A2016/2017 Series T - ^ 6 - 2 .3 - 1 2 - Dual 8192-word x 20-bit Static Cache Memory H IT A C H I/ LOGIC/ARRAYS/MEM The HM62A2016/2017 is a high speed 327680-bit cache memory organized as two banks of 8192

PBII MIL-STD-810E

Abstract: R6C12
Contextual Info: Lucent Technologies Bell Labs Innovations Optimized Reconfigurable Cell Array ORCA ATT2Cxx Series Field-Programmable Gate Arrays Features Description • High-performance, cost-effective 0.5 jim technology (four-input look-up table delay less than 3.6 ns)