0007I Search Results

B272

Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

Contextual Info: MITSUBISHI MICROCOMPUTERS 3886 Group 4\P so'"®9 S IN G L E -C H IP 8 -B IT C M O S M IC R O C O M P U T E R F LA S H M E M O R Y V E R S IO N DESCRIPTION • Power dissipation The 3886 group is the 8-bit m icrocom puter based on the 740 fa m ­ In high-speed m ode . 40 mW

Contextual Info: ispLSI 3256 High Density Programmable Logic Functional Block Diagram A1 OR Array A2 A3 B1 B2 B3 N C0 C1 C2 R D Q F1 Twin GLB F0 D Q E3 D Q E2 D Q E1 Global Routing Pool E0 C3 Output Routing Pool • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE F2 D Q Array

PLSI 1016-60LJ

Abstract: PAL 007 pioneer pal16r8 programming algorithm PAL 008 pioneer lattice 1016-60LJ ISP Engineering Kit - Model 100 PLSI-2064-80LJ GAL16v8 programmer schematic GAL programming Guide ispLSI 2064-80LT
Contextual Info: Lattice Semiconductor Data Book 1996 Click on one of the following choices: • Table of Contents • Data Book Updates & New Products • Go to Main Menu 1996 Lattice Semiconductor Corporation. All rights reserved. ispLSI and pLSI Product Index Pins Density

3256E

Contextual Info: ispLSI 3256E High Density Programmable Logic Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

IC 7481 pin configuration

Contextual Info: MITSUBISHI MICROCOMPUTERS 7480/7481 GROUP .•;• « •:*. ••:•; ^ H P '* * 'i.' * « > * SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DESCRIPTION PIN CONFIGURATION The 7480/7481 group is the single-chip microcomputer adopting the silicon gate CMOS process. In addition to its simple instruction

lattice 1996

Contextual Info: ispLSI and pLSI 2128 ® High-Density Programmable Logic Functional Block Diagram Output Routing Pool ORP Output Routing Pool (ORP) D7 D3 D5 fmax = 100 MHz Maximum Operating Frequency tpd = 10 ns Propagation Delay TTL Compatible Inputs and Outputs Electrically Erasable and Reprogrammable

Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

3256E

Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

Contextual Info: Lattice T'Aie Lattice ispLSI and pLSI 2000 Family ï i I Corporation Features_ J Introduction to ispLSI and pLSI 2000 Family ispLSI and pLSI 2000 Family □ 154 M Hz System Perform ance □ 5.5 ns Pin-to-Pin Delay □ High Density 1,000-6,000 PLD Gates

3192-100LM

Abstract: LSC 132 16*1 3192-70LMI
Contextual Info: Specifications ispLSI and pLSI 3192 ispLSI and pLSI 3192 ® High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: C-Grid m o l e x 2.54mm .10 0 " Pitch C-Grid III Kinked Pin Header FEATURES AND SPECIFICATIONS Features and Benefits • Sizes 1 to 40 circuits Voltage: 350V ■ Easy breakaway to smaller sizes Current: 3 .0 A J ■ Contact and plating orientation according to DIN 4 16 5 1

marking P5t

Abstract: m38022e4sp "SERIES MELPS 740" SERIES MELPS 740 USERS MANUAL transistor da 3807 M38022M4-XXXFP M38022M4-XXXSP capacitor 334 ceramic "MELPS 740" 80P6S-A
Contextual Info: Preface This user’s manual describes M itsubishi’s CMOS 8bit m icrocom puters 3802 Group. A fter reading this m anual, the user should have a through knowledge of the functions and features of the 3802 Group, and should be able to fully utilize the product. The manual starts w ith specifications

si3256

Contextual Info: ispLSI 3256 High Density Programmable Logic Functional Block Diagram A0 A1 OR Array A2 A3 B3 N C0 C1 C2 R F2 D Q F1 Twin GLB F0 D Q D Q E3 E2 D Q E1 Global Routing Pool E0 C3 Output Routing Pool • 100% IEEE 1149.1 BOUNDARY SCAN COMPATIBLE D Q D Q Array

w584

Abstract: V068
Contextual Info: Specifications ispLSI and pLSI 3256 Lattice ispLSrand pLSI 3256 I Semiconductor I Corporation High Density Programmable Logic Features Functional Block Diagram H1GH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect

UAA170

Abstract: UAA180 RBG-1000 IR2406 GBG-1000 OBG-1000 YBG-1000 LM3914 LM3914 PIN uaa17
Contextual Info: SIEMENS RBG-1000 SUPER-RED OBG-1000 YELLOW YBG-1000 GREEN GBG-1000 RED 10 Element Bar Graph Package Dimensions in Inches mm .010 .04 (1.02) typ. (.25) typ. .100 (2.54) typ. .36 (9.14) .30 (7.62) T .15 (3.81) .99(25.15) T J- .20 (5.08) Part Identification Location

3256E

Contextual Info: ispLSI 3256E Device Datasheet June 2010 All Devices Discontinued! Product Change Notifications PCNs have been issued to discontinue all devices in this data sheet. The original datasheet pages have not been modified and do not reflect those changes. Please refer to the table below for reference PCN and current product status.

AA23

Abstract: AC13 AF14 EL B17
Contextual Info: ispLSI 5384V In-System Programmable SuperWide High Density PLD ispDS+™ HDL Synthesis-Optimized Logic Fitter — Supports Leading Third-Party Design Environments for Schematic Capture, Synthesis and Timing Simulation — Static Timing Analyzer and Explore Tool

3256E

Contextual Info: ispLSI 3256E High Density Programmable Logic Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

036 84, 036 85, 036 86 rondorex w21

Abstract: kc 59 246 3256E
Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

logic gates pin configuration

Contextual Info: Specifications ispLSI 3256 ispLSI 3256 High Density Programmable Logic Functional Block Diagram • HIGH PERFORMANCE E CMOS TECHNOLOGY — fmax = 77 MHz Maximum Operating Frequency — tpd = 15 ns Propagation Delay — TTL Compatible Inputs and Outputs

kc 59 246

Abstract: 3256E
Contextual Info: ispLSI 3256E In-System Programmable High Density PLD Functional Block Diagram G3 H0 A0 A1 OR Array A2 A3 ORP ORP • IN-SYSTEM PROGRAMMABLE — 5V In-System Programmable ISP using Lattice ISP or Boundary Scan Test (IEEE 1149.1) Protocol — Increased Manufacturing Yields, Reduced Time-toMarket, and Improved Product Quality

LD3Z

Abstract: INS8070 S807X ins8070-series
Contextual Info: October 1980 INS8070-Series Microprocessor Family General Description Features The IN S8070-Series of m icro p ro ce sso rs h e re in a fte r referred to as the 70-S eries F a m ily is in ten d e d fo r use in system s re q u irin g th e e c o n o m y o f a sin g le ch ip , the

B272

Abstract: 149-IO
Contextual Info: ispLSI 3192 High Density Programmable Logic Features Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 192 I/O Pins — 9000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.