0000CH0 Search Results

Contextual Info: April 1997, ver. 1 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation pci_a MegaCore function implementing a 32-bit peripheral component interconnect PCI interface Optimized for FLEX® 10K architecture Hardware tested

sdram controller

Abstract: SDR SDRAM Controller White Paper PCI_MT32 MegaCore DMA engine
Contextual Info: pci_mt32 MegaCore Function Reference Design September 2002, ver. 1.1 Features Functional Specification 12 • ■ ■ ■ ■ General Description Provides an interface between the Altera pci_mt32 MegaCore function and a 32-bit, 16-MByte SDRAM module Supports 32-bit PCI master and target transactions

C5210

Abstract: 6014-0404-SMT
Contextual Info: llanada 6014-SMT Very Low Profile Side Entry, SMT ! ! J - h w o t— ft l 1 x_ _ \ ii +Í tp B Features * Industiy Standard Phone Jacks with stress relieve mounting pegs. * Material : Glass Filled Polyester, UL 94V-0 Black ‘ Contact : 0.35 mm thick C5210 Alloy

Contextual Info: 8900 SERIES RECEPTACLE Right angle 8901 Series with flanges and hooks U N IT : m m /in c h I8901-XXX-177LX ¡Dimensions Pin ,0 .4 (.0 I6 ) -L : M M ' 1L I r Ir M M'l ! I «- F - _ > A B C D E F 20 2 5 .4 3 (1 .0 0 1 ) 2 0 .3 2

0030h-0033h

Contextual Info: AN 223: PCI-to-DDR SDRAM Reference Design May 2003, ver. 1.0 Introduction Application Note 223 The Altera PCI-to-DDR SDRAM reference design, which you can download to the Stratix PCI development board, provides an interface between the Altera pci_mt64 MegaCore® function and a 64-bit,

amphenol C143

Abstract: amphenol c133
Contextual Info: 705-C133 / 706-C143 SERIES AMPHENOL DIN 41612 TWO-PIECE PRINTED CIRCUIT BOARD CONNECTORS B CONFIGURATION - 2 ROW RECEPTACLE N um ber of C o n tacts 64 32 32 C o n ta c t A rran g em en t ro w , position n um bers Row A & B Fully Loaded Row A Loaded Row A & B Staggered Contact

optiplex

Abstract: Pentium 166 MMX DELL Optiplex vhdl code for 4 channel dma controller dell monitor circuit diagram DELL power supply diagram optiplex 40 pin DELL power supply design of dma controller using vhdl vhdl code for 8 bit ODD parity generator
Contextual Info: November 1999, ver. 3.02 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ A-DS-PCI1-03.02 pci_a MegaCore function implementing a 32-bit peripheral component interconnect PCI master/target interface Optimized for the FLEX® 10K architecture

Contextual Info: PLCC SOCKET ~ SURFACE MOUNT MATERIAL Insulator: Contact: Contact Plating: PLCCSM SERIES Brown PPS UL94V-0 Phosphor Bronze Gold or Tin Over Nickel (see "Plating Option" below) SPECIFICATIONS Current Rating: Insulator Resistance: Contact Resistance: Voltage Rating:

SDR SDRAM Controller White Paper

Abstract: sdram controller DMA engine
Contextual Info: pci_mt32 MegaCore Function Reference Design April 2001, ver. 1.0 Features Functional Specification 12




General Description Provides an interface between the Altera pci_mt32 MegaCore function and a 32-bit, 16-MByte SDRAM module Supports 32-bit PCI master and target transactions

DELL Optiplex

Abstract: EPF10K30AQC208 optiplex
Contextual Info: July 1998, ver. 3 Features Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ A-DS-PCI1-03 pci_a MegaCore function implementing a 32-bit peripheral component interconnect PCI master/target interface Optimized for the FLEX® 10K architecture Extensive hardware testing using:

bsf 84

Abstract: optiplex EPF10K50 EPF10K50RC240 DEC21052-AB EPF10K30AQC208 10KJTAG E2925A
Contextual Info: PCI Master/Target MegaCore Function With DMA Data Sheet 1998年 7 月 ver.3 機能 Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ Altera Corporation A-DS-PCI1-03/J DMA機能付きPCIマスタ／ ターゲットMegaCoreファンクション pci_a は32ビット・ペリフェラル・コンポーネント・インタコネクト PCI

fifo buffer

Abstract: BUFFER FIFO controller for sdram dual port fifo
Contextual Info: pci_mt64 MegaCore Function Reference Design September 2003, ver. 1.2 Features Functional Specification 10 • ■ ■ ■ ■ General Description This reference design shows how to connect the local-side signals of the Altera pci_mt64 MegaCore function to local-side applications when the

BUFFER FIFO

Contextual Info: pci_mt64 MegaCore Function Reference Design November 2000, ver. 1.0 Features Functional Specification 10 • ■ ■ ■ ■ General Description This reference design shows how to connect the local-side signals of the Altera pci_mt64 MegaCore function to local-side applications when the