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74HC109
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Philips Semiconductors
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Dual J invertedK flip-flop with set and reset positive-edge trigger |
Original |
PDF
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57.64KB |
9 |
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74HC109
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Philips Semiconductors
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positive-edge trigger |
Original |
PDF
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50KB |
7 |
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74HC109D
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Philips Semiconductors
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Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger |
Original |
PDF
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57.63KB |
9 |
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74HC109D
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Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
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32.93KB |
1 |
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74HC109D,652
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NXP Semiconductors
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Bulk Pack, CECC |
Original |
PDF
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57.61KB |
9 |
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74HC109D,653
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NXP Semiconductors
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT109-1 (SO16); Container: Reel Pack, SMD, 13", CECC |
Original |
PDF
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57.61KB |
9 |
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74HC109D/AUJ
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Philips Semiconductors
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Logic - Flip Flops, Integrated Circuits (ICs), IC FLIP FLOP DUAL J-K 16SOIC |
Original |
PDF
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9 |
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74HC109DB
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Philips Semiconductors
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Dual J inverted(K) flip-flop with set and reset, positive-edge trigger |
Original |
PDF
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67.49KB |
9 |
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74HC109DB
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|
Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
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32.93KB |
1 |
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74HC109DB,112
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NXP Semiconductors
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Tube |
Original |
PDF
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57.61KB |
9 |
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74HC109DB,118
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NXP Semiconductors
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT338-1 (SSOP16); Container: Reel Pack, SMD, 13" |
Original |
PDF
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57.61KB |
9 |
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74HC109DB-T
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NXP Semiconductors
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V |
Original |
PDF
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57.61KB |
9 |
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74HC109DB-T
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Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
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32.93KB |
1 |
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74HC109D-Q100J
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Nexperia USA
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Uncategorized - Miscellaneous - 74HC109D-Q100/SOT109/SO16 |
Original |
PDF
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790.33KB |
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74HC109D-T
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NXP Semiconductors
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Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V |
Original |
PDF
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57.61KB |
9 |
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74HC109D-T
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|
Unknown
|
Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
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32.93KB |
1 |
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74HC109DW
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Philips Semiconductors
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Dual J inverted(K) flip-flop with set and reset, positive-edge trigger |
Original |
PDF
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67.49KB |
9 |
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74HC109N
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Philips Semiconductors
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Dual J Inverted(K)Flip-flop with Set and Reset, Positive-Edge Trigger |
Original |
PDF
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57.63KB |
9 |
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74HC109N
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|
Unknown
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Historical semiconductor price guide (US$ - 1998). From our catalog scanning project. |
Historical |
PDF
|
32.93KB |
1 |
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74HC109N,652
|
|
NXP Semiconductors
|
Dual JK flip-flop with set and reset; positive-edge trigger - Description: Dual J-/K Flip-Flop with Set and Reset; Positive-Edge Trigger ; Fmax: 75 MHz; Logic switching levels: CMOS ; Output drive capability: +/- 5.2 mA ; Power dissipation considerations: Low Power or Battery Applications ; Propagation delay: 15@5V ns; Voltage: 2.0-6.0 V; Package: SOT38-4 (DIP16); Container: Bulk Pack, CECC |
Original |
PDF
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57.61KB |
9 |