"VLSI TECHNOLOGY" ABSTRACT FOR Search Results

USE OF TRANSISTOR

Abstract: Marquardt Switches transistor model list
Contextual Info: Transistor Abstraction for the Functional Verification of FPGAs Guy Dupenloup, Thierry Lemeunier, Roland Mayr Altera Corporation 101 Innovation Drive San Jose, CA 95134 1-408-544-8672 {gdupenlo, tlemeuni, rmayr}@altera.com ABSTRACT This paper discusses the use of transistor abstraction to enable the

"RF MOSFETs"

Abstract: "vlsi technology" abstract for n channel depletion MOSFET depletion p mosfet RF MOSFETs AN1226 mosfet for different channel length AN1228 n mosfet depletion mosfet p-type
Contextual Info: AN1226 APPLICATION NOTE UNDERSTANDING LDMOS DEVICE FUNDAMENTALS John Pritiskutch - Brett Hanson 1. ABSTRACT This paper focuses on the structural aspects of two basic types of RF power MOSFETS: the DMOS and the LDMOS. The comparison of the DMOS and LDMOS structures reveals the basic fundamentals of the

Contextual Info: Freescale Semiconductor, Inc. Order number: AN1405 Rev 1, 09/2001 APPLICATION NOTE AN1405 ECL Clock Distribution Techniques By: Todd Pearson ECL Applications Engineering ABSTRACT This application note provides information on system design using ECL logic technologies for reducing system clock skew

Contextual Info: MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design using ECL logic technologies for reducing system clock skew

Contextual Info: MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design using ECL logic technologies for reducing system clock skew

flash "high temperature data retention" mechanism

Abstract: Angstrem Hebrew material science and technology 1117 FG 0.18-um CMOS Flash technology DSASW0037374
Contextual Info: SuperFlash Memory Program/Erase Endurance Viktor Markov, Xian Liu, Alexander Kotov, Amitay Levi, Tho Ngoc Dang, and Yuri Tkachev Silicon Storage Technology, Inc., 1171 Sonora Court, Sunnyvale, CA 94086, E-mail: akotov@sst.com Abstract––Program/erase endurance data for SuperFlash

"vlsi technology" abstract

Abstract: magnetic read switch circuit current conveyors BL14 "vlsi technology" abstract for free ieee paper on vlsi
Contextual Info: To be published at VLSI Symposium 2002 A low power 1Mbit MRAM based on 1T1MTJ bit cell integrated with Copper Interconnects M. Durlam, P. Naji, A. Omair, M. DeHerrera, J. Calder, J. M. Slaughter, B. Engel, N. Rizzo, G. Grynkewich, B. Butcher, C. Tracy, K. Smith, K. Kyler, J. Ren, J. Molla, B. Feil, R. Williams, S. Tehrani

"RF MOSFETs"

Abstract: n mosfet depletion depletion p mosfet "vlsi technology" abstract for N CHANNEL DEPLETION MOSFET p channel depletion mosfet RF MOSFETs "vlsi technology" abstract AN1226 n mosfet depletion note
Contextual Info: AN1226 APPLICATION NOTE UNDERSTANDING LDMOS DEVICE FUNDAMENTALS John Pritiskutch - Brett Hanson 1. ABSTRACT This paper focuses on the structural aspects of two basic types of RF power MOSFETS: the DMOS and the LDMOS. The comparison of the DMOS and LDMOS structures reveals the basic fundamentals of the

vhdl projects abstract and coding

Abstract: vhdl convolution coding "vlsi technology" abstract XCV200 Visicom
Contextual Info: Success Story VisiCom Uses Xilinx FPGAs for a Reconfigurable The combination of the Virtex hardware, associated software tools, and engineering process improvements have proven to be a great success. Image Processing Module by Tamara Snowden, Public Relations, Xilinx, tamaras@xilinx.com

Contextual Info: 4. Precautions for 1C Application 1 Absolute maximum ratings This value varies with the amount of 1C integration in package types. The maximum ratings for semiconduc­ tor devices are normally specified by “ absolute maximum ratings" The values shown in the maximum ratings table must

JIS-C-7022

Contextual Info: 4. 1 Precautions for 1C Application Absolute m axim um ratings A g en eral exam ple on the relation with Absolute M axium Ratings. The maximum ratings for semiconductor devices are normally specified by “ absolute maximum ratings” . The values shown in the

TRANSISTOR 30GHZ

Abstract: "vlsi technology" abstract for Marconi Optical Components Bipolar HJ GEC Marconi Materials Technology Schematics 5250 30GHz transistor trench TEOS oxide layer INTERMETal diode
Contextual Info: Process HJ: A 30 GHz NPN and 20 GHz PNP Complementary Bipolar Process for High Linearity RF Circuits. M C Wilson, P H Osborne, S Nigrin, S B Goody, J Green, S J Harrington, T Cook, S Thomas, A J Manson and A Madni Mitel Semiconductor Cheney Manor, Swindon, Wiltshire, SN2 2QW, U.K.

DUSLIC

Abstract: code for echo SICOFI-4 c2ku
Contextual Info: Integrated Digital Line CODEC Architectures: A Tutorial Review Manish Bhardwaj Telecom Devices Signal Processing and Control Division Microelectronics Design Center Infineon Asia Pacific 168 Kallang Way Singapore 349253. e-mail: manish.bhardwaj@infineon.com

bsim3

Abstract: bsim3 circuit model Tech MOS Technology bsim3 model ESSDERC-98 gilbert cell sum harmonicbalance
Contextual Info: A Large Signal Non-Quasi-Static MOS Model for RF Circuit Simulation A.J. Scholten, L.F. Tiemeijer, P.W.H. de Vreede and D.B.M. Klaassen Philips Research Laboratories, Prof. Holstlaan 4, 5656 AA Eindhoven, The Netherlands Phone: +31-40-2742723; Fax: +31-40-2743390; E-mail: andries.scholten@philips.com

Contextual Info: 4. 1 Precautions for 1C Application Absolute m axim um rating s The m axim um ratings fo r sem iconductor devices are norm ally specified by “ absolute maximum ratin gs” . The values shown in the maximum ratings table m ust never be ex­ ceeded even fo r a moment.

tunnel diodes

Abstract: 1E-18 injector tunnel detector ed 39
Contextual Info: Tunneling Phenomenon in SuperFlashâ Cell A.Kotov, A.Levi, Yu.Tkachev, and V.Markov Silicon Storage Technology Inc., 1171 Sonora Court, Sunnyvale, CA 94086, Tel. 408 522-7350, akotov@sst.com Abstract––An extensive investigation of interpoly oxide conduction (erase) mechanism for SuperFlash cell is

mc34063 step down with mosfet

Abstract: abstract of battery charging circuit using scr 1000w class d circuit diagram schematics mc34063 h-bridge igbt pwm schematics circuit MC1466 MC34063 Boost MOSFET 500MHz Frequency Counter Using MECL 10 amp 12 volt solar charger circuits mc34063 solar charger h-bridge igbt pwm schematics circuit
Contextual Info: BR1522/D Rev. 1, Oct-1999 Application Notes, Article Reprints and Engineering Bulletins ON Semiconductor Formerly a Division of Motorola Reference Materials Selector Guide Application Notes, Article Reprints and Engineering Bulletins Reference Materials Selector Guide

Contextual Info: Freescale Semiconductor, Inc. MOTOROLA Order Number: AN1405/D SEMICONDUCTOR TECHNICAL DATA Rev 1, 09/2001 AN1405 ECL Clock Distribution Techniques Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design

"vlsi technology" abstract for

Abstract: TRANSISTOR 30GHZ "vlsi technology" abstract Bipolar HJ 30GHz transistor trench TEOS oxide layer complementary npn-pnp Schematics 5250 SiGe PNP transistor high gain PNP RF TRANSISTOR
Contextual Info: A New Complementary Bipolar Process featuring a Very High Speed PNP. M C Wilson, P H Osborne, S Nigrin, S B Goody, J Green, S J Harrington, T Cook, S Thomas and A J Manson. Mitel Semiconductor Cheney Manor, Swindon, Wiltshire, SN2 2QW, U.K. Abstract This paper introduces "Process HJ" a

bit-slice

Contextual Info: Challenges of CAD Development for Datapath Design Tim Chan, Design Technology, Intel Corp. Amit Chowdhary, Design Technology, Intel Corp. Bharat Krishna, Design Technology, Intel Corp. Artour Levin, Design Technology, Intel Corp. Gary Meeker, Design Technology, Intel Corp.

QUANTUM CAPACITIVE

Abstract: floating-gate 4156C flash "high temperature data retention" mechanism split-gate flash quantum dot
Contextual Info: Detection of Single-Electron Transfer Events and Capacitance Measurements in Submicron Floating-Gate Memory Cells Yuri Tkachev and Alexander Kotov Silicon Storage Technology, Inc. Sunnyvale, USA e-mail: ytkachev@sst.com Abstract—A simple technique for monitoring floating gate

wavelet transform

Abstract: wavelet power system TMS320C40 abstract on RTOS and multitasking Daubechies filter integer "frame grabber"
Contextual Info: DSPS Fest ’99 An Integer Wavelet Transform, Implemented on a Parallel TI TMS320C40 Platform Page 1 AN INTEGER WAVELET TRANSFORM, IMPLEMENTED ON A PARALLEL TI TMS320C40 PLATFORM Francis Decroos1,2, Peter Schelkens1,2, Gauthier Lafruit2, Jan Cornelis1, Francky Catthoor2,3

MC10E111

Abstract: MPC973 10H645 AN1405 E211
Contextual Info: Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Order Number: AN1405/D Rev 1, 09/2001 ECL Clock Distribution Techniques AN1405 Prepared by: Todd Pearson ECL Applications Engineering Abstract This application note provides information on system design

hot electron devices

Abstract: igfet sonos SST superflash Dual-Gate Mosfet electric field permittivity DSASW0037374 superflash sst
Contextual Info: IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 50, NO. 3, MARCH 2003 809 An Analytical Model for Optimization of Programming Efficiency and Uniformity of Split Gate Source-Side Injection Superflash Memory Huinan Guan, Member, IEEE, Dana Lee, Member, IEEE, and G. P. Li