"SENSE AMPLIFIER" VOLTAGE CONTROL CURRENT PRECHARGE MEMORY Search Results

39S256160DT-7

Abstract: HYB39S256400D PC133-222-520 PC166
Contextual Info: Data Sheet, Rev. 1.02, Feb. 2004 HYB39S256400D[C/T] L HYB39S256800D[C/T](L) HYB39S256160D[C/T](L) 256-MBit Synchronous DRAM SDRAM Memory Products N e v e r s t o p t h i n k i n g . Edition 2004-02 Published by Infineon Technologies AG, St.-Martin-Strasse 53,

"sense amplifier" voltage control current precharge memory

Contextual Info: Application 2. Dynamic RAM DRAM 2.1 Features of DRAM DRAM has a simple two-element memory structure, consisting o f a single transistor and a single capacitor. Due to this feature, DRAM is suitable for a higher degree of chip integration and can implement low-price

Contextual Info: GM72V66441ET/ELT 4,194,304 WORD x 4 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66441ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously

GM72V66841ET

Contextual Info: GM72V66841ET/ELT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously

w986432dh

Abstract: 2262 decoder
Contextual Info: PRELIMINARY W986432DH 512K x 4 BANKS × 32 BITS SDRAM GENERAL DESCRIPTION W986432DH is a high-speed synchronous dynamic random access memory SDRAM , organized as 512K words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology,

GM72V66441

Contextual Info: GM72V66441ET/ELT 4,194,304 W O R D x 4 B I T x 4 B A N K SYNCHRONOUS DYNAMIC RAM Description The GM72V66441ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously

2272 decoder

Abstract: GM72V66841ET EIAJ lcdd lpec1
Contextual Info: GM72V66841ET/ELT 2,097,152 WORD x 8 BIT x 4 BANK SYNCHRONOUS DYNAMIC RAM Description The GM72V66841ET/ELT is a synchronous dynamic random access memory comprised of 67,108,864 memory cells and logic including input and output circuits operating synchronously

HYB 39S128160CT-7

Abstract: HYB 39S128800CT-7 HYB 39S128160CT-7.5
Contextual Info: HYB 39S128400/800/160CT L 128-MBit Synchronous DRAM 128-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: -7 -7.5 -8 Units • Automatic and Controlled Precharge Command fCK 143 133 125 MHz • Data Mask for Read/Write Control (x4, x8)

PC133-333

Abstract: P-TSOPII-54 hyb39s64400
Contextual Info: HYB39S64400/800/160A/BT L 64MBit Synchronous DRAM Ultra High Speed 64 MBit Synchronous DRAM PC143 & PC133 • High Performance: -7 -7.5 Units fCKmax. 143 133 MHz tCK3 7 7.5 ns tAC3 5.4 5.4 ns tCK2 10 10 ns tAC2 5.5 6 ns • Fully Synchronous to Positive Clock Edge

Contextual Info: HY57V281620HC 4 Banks x 2M x 16Bit Synchronous DRAM Preliminary DESCRIPTION The Hyundai HY57V281620HC is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V281620HC is organized as 4banks of 2,097,152x16

Contextual Info: HY57V28820HC 4Banks x 4M x 8Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V28820HC is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28820HC is organized as 4banks of

Contextual Info: HY57V28420HC 4Banks x 8M x 4Bit Synchronous DRAM DESCRIPTION The Hyundai HY57V28420HC is a 134,217,728bit CMOS Synchronous DRAM, ideally suited for the main memory applications which require large memory density and high bandwidth. HY57V28420HC is organized as 4banks of

39S256160T

Abstract: P-TSOPII-54
Contextual Info: HYB39S25640x/80x/16xT 256MBit Synchronous DRAM 256 MBit Synchronous DRAM Target Information Rev. 0.5 High Performance: -8 -10 Units fCK 125 100 MHz tCK3 8 10 ns tAC3 6 7 ns tAC2 6 8 ns • Multiple Burst Read with Single Write Operation • Automatic Command

W942516AH

Contextual Info: PRELIMINARY W942516AH 4M x 4 BANKS × 16 BIT DDR SDRAM GENERAL DESCRIPTION W942516AH is a CMOS Double Data Rate synchronous dynamic random access memory DDR SDRAM , organized as 4,194,304 words × 4 banks × 16 bits. Using pipelined architecture and 0.175

39S256160DT-7

Abstract: HYB 39S256160DT-7.5 PC100-222 PC133-222 P-TSOPII-54 P-TSOP-54-2
Contextual Info: HYB39S256400/800/160DT L /DC(L) 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -6 -7 -7.5 -8 Units • Data Mask for Read / Write control (x4, x8) • Data Mask for byte control (x16) • Auto Refresh (CBR) and Self Refresh fCK 166

GM72V281641

Contextual Info: GM72V281641AT/ALT 4Banks x 2M x 16bits Synchronous DRAM Description TheGM72V281641AT/ALT is a synchronous dynamic random access memory comprised of 134,217,728 memory cells and logic including input and output circuits operating synchronously by referring to the positive edge of the externally

MARKING CAW

Abstract: P-TSOPII-54
Contextual Info: HYB39S256400/800/160CT L 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -7.5 -8 -8A Units fCK 133 125 125 MHz tCK3 7.5 8 8 ns tAC3 5.4 6 6 ns tCK2 10 10 12 ns tAC2 6 6 6 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature

W941232AD

Contextual Info: W941232AD 1M x 4 BANKS × 32 BIT DDR SDRAM 1. GENERAL DESCRIPTION W941232AD is a CMOS Double Data Rate synchronous dynamic random access memory DDR SDRAM , organized as 1,048,576 words × 4 banks × 32 bits. Using pipelined architecture and 0.175 µm process technology, W941232AD delivers a data bandwidth of up to 800M words per second (-5).

Hitachi DSA00276

Contextual Info: HM5257165B-75/A6 HM5257805B-75/A6 HM5257405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1237A Z Rev. 1.0 Dec. 11, 2000 Description The Hitachi HM5257165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The

Contextual Info: HM5259165B-75/A6 HM5259805B-75/A6 HM5259405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0118H10 Ver. 1.0 Apr. 6, 2001 Description The HM5259165B is a 512-Mbit SDRAM organized as 8388608-word × 16-bit × 4 bank. The HM5259805B

Contextual Info: HM5257165B-75/A6 HM5257805B-75/A6 HM5257405B-75/A6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM E0081H10 1st edition (Previous ADE-203-1237A (Z) Jan. 31, 2001

Hitachi DSA00164

Contextual Info: HM5251165B-75/A6/B6 HM5251805B-75/A6/B6 HM5251405B-75/A6/B6 512M LVTTL interface SDRAM 133 MHz/100 MHz 8-Mword x 16-bit × 4-bank/16-Mword × 8-bit × 4-bank /32-Mword × 4-bit × 4-bank PC/133, PC/100 SDRAM ADE-203-1095 Z Preliminary Rev. 0.0 Sep. 1, 1999

PC100-322-620

Abstract: 39S256 PC133 registered reference design HYB 39S256400CT-7.5 PC-100-322-620
Contextual Info: HYB39S256400/800/160CT L 256MBit Synchronous DRAM 256 MBit Synchronous DRAM • High Performance: -7.5 -8 -8A Units fCK 133 125 125 MHz tCK3 7.5 8 8 ns tAC3 5.4 6 6 ns tCK2 10 10 12 ns tAC2 6 6 6 ns • Fully Synchronous to Positive Clock Edge • 0 to 70 °C operating temperature

39S256160T

Abstract: PC100-322-620 MARKING AX5 SMD MARKING T20
Contextual Info: HYB 39S256400/800/160T 256-MBit Synchronous DRAM 256-MBit Synchronous DRAM • Multiple Burst Read with Single Write Operation • High Performance: • Automatic and Controlled Precharge Command -7.5 -8 -8A -8B Units fCK 133 125 125 100 MHz tCK3 7.5 8 8 10