"PROCESSOR" "SHIFT REGISTER" ALU Search Results

TA 7136 p

Abstract: weitek 7137-100-G ad 7137
Contextual Info: WTL 7137 32-BIT INTEGER PROCESSOR ADVANCE DATA Features 32-BIT, SINGLE-CHIP PROCESSOR o 3 2-bit Integer ALU o 4-port 36x32 Register File o Parallel Multiply/Divide Unit o 32-bit Shift/Field Merge Unit POWERFUL INSTRUCTION SET o Add, Subtract, Multiply, Divide

weitek

Abstract: P11000 ta 7136 AD27 AD29 AD30 32-bit-Integer weitek 7137 weitek 7136 TA 7136 p
Contextual Info: WTL 7137 32-BIT INTEGER PROCESSOR ADVANCE DATA APRIL, 1986 Features 32-BIT, SINGLE-CHIP PROCESSOR o 3 2-bit Integer ALU o 4-port 36x32 Register File o Parallel Multiply/Divide Unit o 32-bit Shift/Field Merge Unit POWERFUL INSTRUCTION SET o Add, Subtract, Multiply, Divide

TI L8236

Abstract: weitek L-8237 XL-8200 l8236
Contextual Info: XL-8237 32-BIT RASTER IMAGE PROCESSOR PRELIMINARY DATA M ay 1988 Features 32-BIT, SINGLE-CHIP GRAPHICS PROCESSOR HIGH PERFORMANCE 32-bit integer ALU Four-port 3 6 x 3 2 register file Parallel multiply/divide unit for Bezier computation 32-bit shift/field merge unit for BitBlt

XL-8137

Abstract: Weitek xl-8137 XL8137
Contextual Info: XL-8137 32-BIT INTEGER PROCESSING UNIT DATA SHEET January 1989 Features 32-BIT, SIN G LE-CH IP PROCESSOR THREE-ADDRESS ARCHITECTURE 32-bit Integer ALU F our-port 36x32 Register File Parallel M ultiply/Divide Unit 32-bit Shift/Field M erge U nit Source an d destination registers are specified independ­

SN74AS888

Abstract: AS888 CI 4016 SN74AS888-1 srf 2338 "Overflow detection"
Contextual Info: SN54AS888, SN74AS888 8-BIT PROCESSOR SLICES MARCH 1985-REVISED JANUARY 1986 • STL-AS Technology • Full Carry Look Ahead Support Parallel a-Bit ALU with Expansion Inputs and Outputs • Sign, Carry Out, Overflow, and Zero-Detect Status Capabilities 13 Arithmetic and Logic Functions

TMS320F206 load program

Abstract: C2xx DCm240 EZ76 HCL 0300 C203 F206 TMS320 TMS320C203 TMS320C209
Contextual Info: TMS320F206 DIGITAL SIGNAL PROCESSOR • High-Performance Static CMOS Technology 32-Bit ALU/Accumulator • Includes the T320C2xLP Core CPU 16 x 16-Bit Multiplier With a 32-Bit Product • TMS320F206 is a Member of the TMS320C2xx Generation That Also Includes the TMS320C203, TMS320C204,

RRUS 32

Abstract: RRUS 32 b2 RRUS 01 B1 RRUS 01 B2 2101S 68000 thomson
Contextual Info: fi?]> D S G S-THONSON 87D 08679 D § 7cl5cia37_DDDflt17c] r - i f j - n . o s - TS68930 • TS68931 ADVANCE INFORMATION HMOS2 The T S 68930/1 Programmable S ignal Processor is a high-speed general purpose signal and arithm etic processo'r w ith on-chip memory, m u ltip lier, ALU, accumulators and l/O s . It is organized in

Contextual Info: TMS320F206 DIGITAL SIGNAL PROCESSOR S PR S050-N O VEM BER 1996 H i g h - P e r f o r m a n c e Static C M O S T e c hn o l o g y • 3 2- Bi t ALU / A c c u m u l a t o r • I n c l ud e s the T 3 2 0 C 2 x L P Cor e CPU • 16 x 1 6- Bi t Mul t i pl i er With a 3 2- Bi t P r o d u c t

4057A

Abstract: CD4057AD CD4057A CD4067A
Contextual Info: 4û 5'7A CD4057A Types CMOS LSI 4-Bit Arithmetic Logic Unit The RCA-CD4057A is a low-power arithme­ tic logic unit ALU designed for use in LSI computers. An arithmetic system of virtually any size can be constructed by wiring to­ gether a number of CD4057A ALU's. The

kbaa

Abstract: amd 2901 alu weitek FPU wtl3332 weitek WTL3164 amd 2901 Kaaa 3332 weitek CRTN 1010
Contextual Info: / CHRIS1 EMBEDDED PROCESSOR UNIT EPU February 1988 FEATURES • 32-Bit RISC Architecture • 2901 ALU Superset • 20 MIPS Throughput • 32-Bit ALU or 2 16-Bit ALUs • Executes 1 1nstruction/Cycle • 2910 Sequencer Superset • 3Kb WCS Instruction Cache

addressing modes in adsp-21xx

Abstract: ADSP21XX block diagram addressing modes of adsp 21xx processors direct addressing mode in adsp-21xx EPROM 2764 ADSP-21xx block diagram ADSP-2106
Contextual Info: ANALOG DEVICES ADSP-2100 Family DSP Microcomputers ADSP-21XX FUNCTIONAL BLOCK DIAGRAM SUM M ARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

addressing modes in adsp-21xx

Abstract: i3 i5 i7 processor ADSP-2101 ADSP-2105 ADSP-2111 ADSP-2115 PMD70 "saturation instruction" "saturation" "instruction"
Contextual Info: ALU ADD / ADD with CARRY Syntax: [ IF cond ] Permissible xops AX0 MR2 AX1 MR1 AR MR0 SR1 SR0 AR AF = xop Permissible yops AY0 AY1 AF + + + + + yop C yop + C constant constant + C 15 ; Permissible conds see Table 15.9 EQ LE AC NE NEG NOT AC GT POS MV GE AV

RRUS 01 B1

Abstract: RRUS 32 b2 RRUS 01 B2 ocular lcd e purse TS68930 TS68931 TSSB831 RRUS 01 3BS1
Contextual Info: T S 6 8 9 3 0 • T S 68931 ADVANCE INFORMATION HMOS2 The T S 6 8 9 3 0 /1 Programmable Signal Processor is a high-speed general purpose signal and arithm etic processor w ith on-chip memory, m ultiplier, ALU, accumulators and I/O s . It is organized in

i3 i5 i7 processor

Abstract: i5 instruction set addressing modes in adsp-21xx i3 processor M6 transistor m7 diode ADSP-2100 ADSP-2181
Contextual Info: 15 Instruction Set Reference Multifunction Instructions <ALU>*† , <MAC>*† AX0 AX1 MX0 MX1 AX0 AX1 MX0 MX1 = DM <ALU>* <MAC>* <SHIFT>* = DM ( I0 I1 I2 I3 , dreg , , , , = I0 I1 I2 I3 , , , , M0 , M1 M2 M3 DM ( PM ( DM ( PM ( <ALU>* <MAC>* <SHIFT>* I0

A0-A13

Abstract: D2322 P68AK
Contextual Info: BACK a Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

D2322

Abstract: ADSP-2100 ADSP2104 ADSP-2104 ADSP-2104L ADSP-2109 eprom 2764 "vector instructions" saturation
Contextual Info: a Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/

HA 13645

Abstract: CD4067A cd4057 CD4057AH CD4057AD CD4057AK CD40B IMD14 transistor s912 16 bit alu circuit design
Contextual Info: HARRIS SEMICOND SECTOR 37E D M3G2271 DÜSIMST S « H A S 3875081 G E SOLID STATE 0 1E 13645 T - m - n CD4057A Types CMOS LSI 4-Bit Arithmetic Logic Unit The RCA-CD4057A is a low-power arithme­ tic logic unit ALU designed for use in LSI computers. An arithmetic system of virtually

0795a

Abstract: Amu interface lode dsp galois ALU of 4 bit adder and subtractor
Contextual Info: Features • Two multiplier accumulator units • • • • • • • • • • • • • • • • – Single cycle 16 x 16-bit signed and unsigned multiply - accumulate 40-bit arithmetic logical unit ALU Four 40-bit accumulators (32-bit + 8 guard bits)

HA 13645

Abstract: CD4057 cd4057a
Contextual Info: HARRIS SEMICOND SECTOR 37E D M3G2271 DÜSIMST S « H A S 3875081 G E SOLID STATE 0 1E 13645 T - m - n CD4057A Types CMOS LSI 4-Bit Arithmetic Logic Unit The RCA-CD4057A is a low-power arithme­ tic logic unit ALU designed for use in LSI computers. An arithmetic system of virtually

ARM processor

Abstract: ARM processor data sheet ARM PROCESSOR DATASHEET arm 5 datasheet arm 7 data sheet ARM710 ARM7500
Contextual Info: 1 5 11 ARM Processor Instruction Set 5.1 Instruction set summary 5-2 5.2 The condition field 5-3 5.3 Branch and branch with link B, BL 5-4 5.4 Data processing 5-6 5.5 PSR transfer (MRS, MSR) 5-15 5.6 Multiply and multiply-accumulate (MUL, MLA) 5-20 5.7 Single data transfer (LDR, STR)

arm processor

Abstract: mcr 5102 basic architecture of ARM Processors ARM710 ARM7500FE PSR 57-3 Basic ARM hardware
Contextual Info: 1 5 11 ARM Processor Instruction Set This chapter describes the ARM processor instruction set. 5.1 Instruction Set Summary 5-2 5.2 The Condition Field 5-2 5.3 Branch and Branch with Link B, BL 5-3 5.4 Data Processing 5-4 5.5 PSR Transfer (MRS, MSR) 5-13

ARM processor data sheet

Abstract: ARM7 instruction set ARM processor ARM7100 specification of ldr SWP-1 ARM processors data sheet basic architecture of ARM Processors
Contextual Info: 1 11 ARM Processor Instruction Set 5 5.1 Instruction Set Summary 5-2 5.2 The Condition Field 5-3 5.3 Branch and Branch with link B, BL 5-4 5.4 Data Processing 5-6 5.5 PSR Transfer (MRS, MSR) 5-15 5.6 Multiply and Multiply-Accumulate (MUL, MLA) 5-19 5.7 Single Data Transfer (LDR, STR)

2164 dynamic ram

Abstract: ADSP-2165 ADSP-2100 ADSP-2101 ADSP-2103 ADSP-2161
Contextual Info: a SUMMARY 16-Bit Fixed-Point DSP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus and Dual Data Buses Independent Computation Units: ALU, Multiplier/ Accumulator and Shifter Single-Cycle Instruction Execution and Multifunction

5-pin BMS

Abstract: 27c256 plcc "vector instructions" saturation T 2109
Contextual Info: ANALOG DEVICES Low Cost DSP Microcomputers ADSP-2104/ADSP-2109 FUNCTIONAL BLOCK DIAGRAM SUM M A RY 16-Bit Fixed-Point D SP Microprocessors with On-Chip Memory Enhanced Harvard Architecture for Three-Bus Performance: Instruction Bus & Dual Data Buses Independent Computation Units: ALU, Multiplier/