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ATL010A0X43-SRZ GE Critical Power ATL010A0X43-SR Non-Isolated Power Module 12Vdc, Programmable
HCTS299KMSR Intersil Corporation HCT SERIES, 8-BIT BIDIRECTIONAL PARALLEL IN PARALLEL OUT SHIFT REGISTER, TRUE OUTPUT, CDFP20
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HSP9501JC-25 Intersil Corporation 10-BIT, DSP-PIPELINE REGISTER, PQCC44

88E1111 PHY registers Datasheets Context Search

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2006 - 88E1111

Abstract: Marvell PHY 88E1111 Datasheet marvell 88E1111 register RGMII sgmii marvell 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 layout Marvell 88E1112 88E1112 Marvell 88E1111
Text: Oscillator 2 88E1111 PHY 88E1112 PHY SGMII MAC Device SMA Marvell 88E1112/1118 Evaluation , 1, is transferred from the PHY to the MAC to signal the change of the control information. This is , . Instead of the ability advertisement, the PHY sends the control information via its tx_config_Reg[15:0 , interoperability tests between a LatticeSCTM device and the Marvell 88E1111 /88E1112 devices. Specifically, this , 88E1111 / 88E1112 devices. · SGMII Physical Layer Interoperability testing of the LatticeSC and Marvell


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PDF TN1127 22-wire 10Mbps, 100Mbps 1000Mbps 88E1111/88E1112 1-800-LATTICE 88E1111 Marvell PHY 88E1111 Datasheet marvell 88E1111 register RGMII sgmii marvell 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 layout Marvell 88E1112 88E1112 Marvell 88E1111
2007 - 88E1111

Abstract: 88E1111 "mdio registers" Marvell PHY 88E1111 88E1111 RGMII config Marvell 88E1111 mdio Marvell PHY 88E1111 alaska sgmii marvell 88e1111 88E1111 BCC package 88E1111 GMII config 88E1111 PHY registers
Text: single-port PHY ( 88E1111 ) Alaska single-port PHY ( 88E1111 ) Fig 2. Alaska Single-Port GbE , Marvell Alaska 88E1111 Single-Port Gigabit Ethernet Transceiver PRODUCT OVERVIEW The Marvell® Alaska® 88E1111 is a physical layer device containing a single Gigabit Ethernet (GbE) transceiver. The , standard CAT 5 unshielded twisted pair. Of Marvell's single-port GbE transceivers, the 88E1111 offers the most flexible Media Access Controller (MAC) interface options. The 88E1111 supports the Gigabit Media


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PDF 88E1111 88E1111 1000BASE-T, 100BASE-TX, 10BASE-T 88E1111-002 88E1111 "mdio registers" Marvell PHY 88E1111 88E1111 RGMII config Marvell 88E1111 mdio Marvell PHY 88E1111 alaska sgmii marvell 88e1111 88E1111 BCC package 88E1111 GMII config 88E1111 PHY registers
2009 - Marvell 88e1111 register map

Abstract: 88E1111 config 88E1111 88E1111 PHY registers map 88E1111 register map 88E1111 registers 88E1111 jumbo 88E1111 GMII config Marvell PHY 88E1111 alaska register map 88E1111 RGMII config
Text: Ethernet interoperability test between a LatticeECP3TM device and the Marvell 88E1111 PHY . Specifically , 's Guide. An external SmartBits box auto-negotiates and transmits BASE-T frames to the Marvell 88E1111 PHY , MAC to the 88E1111 . 88E1111 Hardware Configuration options such as PHY address, HWCFG_MODE and , JTAG J12 SW1 RESET 12V J37 88E1111 Tri-Speed Ethernet MAC SGMII Registers 2 , device and the Marvell 88E1111 PHY . This interoperability tests the correct processing of Gigabit


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PDF 1000BASE-X) TN1196 1000BASE-X 88E1111 H0020 Marvell 88e1111 register map 88E1111 config 88E1111 PHY registers map 88E1111 register map 88E1111 registers 88E1111 jumbo 88E1111 GMII config Marvell PHY 88E1111 alaska register map 88E1111 RGMII config
2004 - MV-S100649-00

Abstract: Marvell 88e1111 register map Marvell PHY 88E1111 Marvell PHY 88E1111 application note 88E1111 88E1111 PHY registers map marvel phy 88e1111 reference design Marvell 88E1111 application note Marvell 88E1111 88E1111 full
Text: CONFIDENTIAL 88E1111 Datasheet Doc. No. MV-S100649-00, Rev. F December 3, 2004 7vu31zzfnua , NDond A# uc 02 tor, 13 In 03 c. 88E1111 Integrated 10/100/1000 Ultra Gigabit Ethernet Transceiver • • The 88E1111 device incorporates the Marvell Virtual Cable Tester™ (VCTâ , 88E1111 device detects and reports potential cabling issues such as pair swaps, pair polarity and , cable and report accurately within one meter the distance to the fault. The 88E1111 device supports the


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PDF 88E1111 MV-S100649-00, 7vu31zzfnua-e4681dge MV-S100649-00 Marvell 88e1111 register map Marvell PHY 88E1111 Marvell PHY 88E1111 application note 88E1111 PHY registers map marvel phy 88e1111 reference design Marvell 88E1111 application note Marvell 88E1111 88E1111 full
2006 - 88E1111

Abstract: 88E1118 88E1112 sgmii specification ieee Marvell PHY 88E1111 Datasheet 88e111 Marvell PHY 88E1111 layout Marvell 88E1111 88E1111 PHY registers 88E1111 "mdio registers"
Text: 88E1112 registers . Figure 6 illustrates the Phy Register Control Panel. Figure 5. ALASKA Virtual Cable , RJ45 88E1111 PHY On-board Oscillator 88E1112 PHY SGMII MAC Device SMA Marvell 88E1112 , LatticeECP2M SGMII solution status signals and registers and the Marvell PHY Register Panel (see Figure 6). The , 1, is transferred from the PHY to the MAC to signal the change of the control information. This is , . Instead of the ability advertisement, the PHY sends the control information via its tx_config_Reg[15:0


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PDF TN1133 22-wire 10Mbps, 100Mbps 1000Mbps 88E1111/88E1112 1-800-LATTICE 88E1111 88E1118 88E1112 sgmii specification ieee Marvell PHY 88E1111 Datasheet 88e111 Marvell PHY 88E1111 layout Marvell 88E1111 88E1111 PHY registers 88E1111 "mdio registers"
2002 - Marvell PHY 88E1111 layout

Abstract: 88E1111 PHY registers 88E1111 88E1111 layout 88e1111 board layout 88e1111 phy mii EVALUATION BOARD 88E1111 88E1111 and SFP applications 88e1111 mii 88E1111 SFP
Text: single-port 88E1111 product performs all of the physical layer ( PHY ) functions for half- and full-duplex , PHY ( 88E1111 ) MAC Interface Options: ¥ GMII/MII ¥ RGMII ¥ SGMII ¥ TBI ¥ RTBI ¥ Serial , Single-Port PHY ( 88E1111 ) Serial Interface Fiber Optics Media Types: ¥ 1000BASE-LX ¥ 1000BASE , Transceiver Solutions Alaska® Single-Port Gigabit Ethernet Transceiver 88E1111 PRODUCT , volume production. The Alaska single-port 88E1111 transceiver leads the industry with the lowest power


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PDF 88E1111 88E1111 10BASE-T 100BASE-TX 1000BASE-T 88E1111-001 Marvell PHY 88E1111 layout 88E1111 PHY registers 88E1111 layout 88e1111 board layout 88e1111 phy mii EVALUATION BOARD 88E1111 88E1111 and SFP applications 88e1111 mii 88E1111 SFP
2009 - Marvell 88e1111 register map

Abstract: 88E1111 PHY registers map 88E1111 88E1111 register map 88E1111 config 88E1111 registers Marvell PHY 88E1111 alaska register map Marvell PHY 88E1111 MDIO read write sfp Marvell 88E1111 application note Marvell PHY 88E111 alaska
Text: between a LatticeECP3TM device and the Marvell 88E1111 PHY . Specifically, the document discusses the following topics: · Overview of LatticeECP3 devices and Marvell 88E1111 PHY · SGMII physical/MAC layer , auto-negotiates and transmits BASE-T frames to the Marvell 88E1111 PHY via the RJ45 connector. The Marvell PHY , the Alaska Ultra 88E1111 Data Sheet for further information on programmable registers . Table 1 , Tri-Speed Ethernet MAC SGMII Registers 2 Marvell PHY U12 Len pkt_gen 8 SW14


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PDF TN1197 88E1111 H0020 Marvell 88e1111 register map 88E1111 PHY registers map 88E1111 register map 88E1111 config 88E1111 registers Marvell PHY 88E1111 alaska register map Marvell PHY 88E1111 MDIO read write sfp Marvell 88E1111 application note Marvell PHY 88E111 alaska
2007 - 88E1111

Abstract: 88E1118 88E1112 Marvell PHY 88E1118 Marvell PHY 88E1111 Datasheet Alaska Ultra 88E1111 Marvell PHY 88E1111 layout Marvell 88E1112 Marvell 88E1111 Gigabit 88E1118
Text: , the PHY Register Control Panel is used instead to control and monitor the 88E1112 registers . Figure 6 , : LFE2M35-FF672 RJ45 MDIO 1000BASE-X 1000BASE-T TX RX 2 2 RJ45 88E1111 PHY On-board Oscillator , interoperability test between a LatticeECP2MTM device and the Marvell® Alaska® Ultra 88E1111 / 88E1112 devices. The , Ultra 88E1111 / 88E1112 devices · 1000BASE-X physical layer interoperability setup and results , Reconciliation GMII PCS PMA PHY PMD MDI Medium 1000 Mbps According to the 802.3-2002 standard, two


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PDF TN1163 1000BASE-X 88E1111/ 88E1112 88E1111/88E1112 1-800-LATTICE 88E1111 88E1118 Marvell PHY 88E1118 Marvell PHY 88E1111 Datasheet Alaska Ultra 88E1111 Marvell PHY 88E1111 layout Marvell 88E1112 Marvell 88E1111 Gigabit 88E1118
2008 - 88E1111 PHY registers map

Abstract: Marvell PHY 88E1111 Datasheet Marvell PHY 88E1111 application note Marvell PHY 88E1111 MDIO read write 88E1111 register map Marvell PHY 88E1111 Xilinx Marvell PHY register map 88E1111 88E1111 register Marvell 88e1111 register map
Text: Ethernetlite peripheral does not provide any mechanism to access the Ethernet PHY registers . These registers , provides reference systems and associated software to access PHY registers by connecting the serial , appropriate PHY configuration registers . Many Ethernet MACs will provide a mechanism for the software to access the registers of the PHY to which it is connected. Because the goal of the XPS Ethernetlite core is to provide a small, simple Ethernet controller, it does not provide access to the PHY registers


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PDF XAPP1042 notes/xapp1042 ppc405. 88E1111 PHY registers map Marvell PHY 88E1111 Datasheet Marvell PHY 88E1111 application note Marvell PHY 88E1111 MDIO read write 88E1111 register map Marvell PHY 88E1111 Xilinx Marvell PHY register map 88E1111 88E1111 register Marvell 88e1111 register map
2008 - 88E1111

Abstract: Marvell PHY 88E1111 Datasheet Marvell PHY 88E1118 Marvell 88E1112 Marvell 88E1111 88E1118 Marvell PHY 88E1118 Datasheet Marvell PHY 88E1111 layout 88E1112 88e111
Text: Oscillator 88E1111 PHY 88E1112 PHY Marvell88E1112/1118 Evaluation Board 8 2 SC_REFCLK , Reconciliation GMII PCS PMA PHY PMD MDI Medium 1000 Mbps According to the 802.3-2002 standard, two , repeater unit to a gigabit PHY . While conformance with implementation of this interface is not strictly , a LatticeSCTM device and the MARVELL 88E1111 /88E1112 devices. Specifically, this technical note discusses the following topics: · Overview of LatticeSC devices and MARVELL AlaskaTM Ultra 88E1111 / 88E1112


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PDF TN1120 88E1111/88E1112 1-800-LATTICE 88E1112 88E1111 Marvell PHY 88E1111 Datasheet Marvell PHY 88E1118 Marvell 88E1112 Marvell 88E1111 88E1118 Marvell PHY 88E1118 Datasheet Marvell PHY 88E1111 layout 88e111
2008 - sgmii marvell 88e1111

Abstract: 88E111* HWCFG_MODE Marvell PHY 88E1111 footprint 88e1111 board layout Marvell+PHY+88E1111+schematic Alaska Ultra 88E1111 Integrated Gigabit Ethernet 88E1111 current Marvell PHY 88E1111 schematic
Text: interface with the device address 0xA6. For details of PHY IC registers in 88E1111 , see Marvell document , . It can operate in 10/100/1000 Base-T with SGMII interface by reconfiguration of the PHY within the , Configuration ( PHY Two-Wire Address 0xA6) Register 27 Bits 3:0 Field HWCFG_ MODE Mode R/W Description Changes to these bits are disruptive to the normal operation; hence, any changes to these registers must be , of Gigabit Ethernet PHY inside the copper SFP. It is pulled up within the module with a 4.7 ­ 10 K


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PDF LCP-1250RJ3SR RJ-45 GBIC-1250RJ3SR, 1250Mb/s, LCP-1250RJ3SR-S, AT24C01A/02/04/08/16 88E1111 sgmii marvell 88e1111 88E111* HWCFG_MODE Marvell PHY 88E1111 footprint 88e1111 board layout Marvell+PHY+88E1111+schematic Alaska Ultra 88E1111 Integrated Gigabit Ethernet 88E1111 current Marvell PHY 88E1111 schematic
2006 - 88E1111

Abstract: Marvell PHY 88E1111 layout 88E1111 schematic sgmii specification ieee sgmii marvell 88E1111 Alaska Ultra 88E1111 Integrated Gigabit Ethernet Marvell 88E1111 Marvell PHY 88E1111 Datasheet 88E1111 GBIC SGMII Marvell PHY 88E1111 schematic
Text: details of PHY IC registers in 88E1111 , see Marvell document "Alaska Ultra 88E1111 Integrated Gigabit , Gigabit PHY device is integrated internally Internal PHY IC is configurable by host system software via , configure the PHY device inner LCP-1250RJ3SR-S via SFP two-wire-interface. Dec. 18. 2006 Rev. 1.01 , PHY within the SFP. 2. This part uses the SFP's Rx-Los pin for link indication and 1000 Base-T , by reconfiguration of the PHY within the SFP. 3. This part supports the 10/100/1000 Base-T with


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PDF LCP-1250RJ3SR-S 1000BASE-T) LCP-1250RJ3SR-S 1250Mb/s, LCP-1250RJ3SR-L, AT24C01A/02/04/08/16 88E1111 Marvell PHY 88E1111 layout 88E1111 schematic sgmii specification ieee sgmii marvell 88E1111 Alaska Ultra 88E1111 Integrated Gigabit Ethernet Marvell 88E1111 Marvell PHY 88E1111 Datasheet 88E1111 GBIC SGMII Marvell PHY 88E1111 schematic
2003 - Marvell 88E1111

Abstract: Marvell PHY 88E1111 footprint 88E1111 Marvell PHY 88E1111 8-port GbE PHY Marvell 88E1111 mdio Marvell PHY 88E1111 PCB Marvell PHY 88E1111 alaska 88E1145 88E1111 alaska
Text: , including to the 88E1145 quad-port Gigabit PHY and the 88E1111 single-port PHY . Allows triple-speed , one 88E1111 Single-Channel PHY . The 88E6151 switchÕs high integration, low power, and glueless , ) GbE Switch 8 x SERDES SERDES 4 x SERDES SERDES Marvell¨ 88E1111 GbE Cu PHY SERDES Marvell 88E1111 GbE Cu PHY SERDES Marvell 88E1111 GbE Cu PHY SERDES Marvell 88E1111 GbE Cu PHY SERDES Marvell 88E1111 GbE Cu PHY 1 GbE 1 GbE 1 GbE 1 GbE 1 GbE Fig 3


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PDF 88E6151/88E6181 88E6151 88E6181 88E6151) 88E6181) 88E6151/81-001 Marvell 88E1111 Marvell PHY 88E1111 footprint 88E1111 Marvell PHY 88E1111 8-port GbE PHY Marvell 88E1111 mdio Marvell PHY 88E1111 PCB Marvell PHY 88E1111 alaska 88E1145 88E1111 alaska
2007 - rj45 120 ohm connector

Abstract: 88E1111 register 88e1111 SGMII mode 88e1111 board layout 88E1111 layout 88E1111 current
Text: interface with the device address 0xA6. For details of PHY IC registers in 88E1111 , see Marvell document , . It can operate in 10/100/1000 Base-T with SGMII interface by reconfiguration of the PHY within the , Configuration ( PHY Two-Wire Address 0xA6) Register 27 Bits 3:0 Field HWCFG_ MODE Mode R/W Description Changes to these bits are disruptive to the normal operation; hence, any changes to these registers must be , of Gigabit Ethernet PHY inside the copper SFP. It is pulled up within the module with a 4.7 ­ 10 K


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PDF LCP-1250RJ3SR RJ-45 GBIC-1250RJ3SR, 1250Mb/s, LCP-1250RJ3SR-S, AT24C01A/02/04/08/16 88E1111 rj45 120 ohm connector 88E1111 register 88e1111 SGMII mode 88e1111 board layout 88E1111 layout 88E1111 current
2007 - 88E111* HWCFG_MODE

Abstract: Marvell PHY 88E1111 schematic 88E1111 PHY register 24 Marvell PHY 88E1111 0xac marvell ethernet switch sgmii MARV 88E1111 schematic 88e1111 SGMII mode Marvell alaska 88E1111 88E111
Text: device address 0xAC. For details of PHY IC registers in 88E1111 , see Marvell document "Alaska Ultra , -1250RJ3SR-S supports the SGMII interface without clock on MAC side. Gigabit PHY device is integrated internally Internal PHY IC is configurable by host system software via SFP 2-wire-interface. Description The LCP , configure the PHY device inner LCP-1250RJ3SR-S via SFP two-wire-interface. The SGMII interface without clock , with SGMII interface by reconfiguration of the PHY within the SFP. 2. This part uses the SFP's Rx-Los


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PDF LCP-1250RJ3SR-S 1000BASE-T) LCP-1250RJ3SR-S h1250RJ3SR-L, GBIC-1250RJ3SR, 1250Mb/s, AT24C01A/02/04/08/16 88E1111 88E111* HWCFG_MODE Marvell PHY 88E1111 schematic 88E1111 PHY register 24 Marvell PHY 88E1111 0xac marvell ethernet switch sgmii MARV 88E1111 schematic 88e1111 SGMII mode Marvell alaska 88E1111 88E111
2008 - marvel phy 88e1111 reference design

Abstract: 88E6182 RGMII switch Marvell PHY 88E1111 alaska register map 88E1111 PHY registers map MSC8156ADS 88E1111 PHY registers map Triple-Speed Ethernet M 88E1111 register map 88E1111 config 88E1111 RGMII
Text: family TDM bus. 2.2.1 RGMII Port: PHY Two Marvell 88E1111 single GETH PHYs serve the MSC8156 , accesses Switch internal registers or an external PHY . MDC buffers isolate MDC_DSP signals upon SRESET , phy 88E1111 phy FPGA MII TS3L110RGYR x 2 MSC815x MI nMIIdsp MI Bus Switch MI , . . . . . . . . . . . 2-2 2.2.1 RGMII Port: PHY . . . . . . . . . . . . . . . . . . . . . . . . . . . , . . . . . . . . . . . . . . . . . 2-38 2.16.7 Test Page Registers TR . . . . . . . . . . . . . . . .


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PDF MSC8156ADS MSC8156 MSC8256 MSC8156ADSRM EL516 marvel phy 88e1111 reference design 88E6182 RGMII switch Marvell PHY 88E1111 alaska register map 88E1111 PHY registers map 88E1111 PHY registers map Triple-Speed Ethernet M 88E1111 register map 88E1111 config 88E1111 RGMII
2006 - Not Available

Abstract: No abstract text available
Text: details of PHY IC registers in 88E1111 , see Marvell document “Alaska Ultra 88E1111 Integrated Gigabit , PHY device is integrated internally Operating with single +3.3 V power supply Compatible to both shielded and unshielded twisted pair Cat5 cable Internal PHY IC is configurable by host system software , enhance, the software can configure the PHY device inner LCP-1250RJ3SR-S via SFP two-wire-interface , between a 10/100/1000 PHY and a MAC with significantly less signal pins than required for GMII. 2).


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PDF LCP-1250RJ3SR-S LCP-1250RJ3SR-S 1000Mb/s RJ-45 LCP-1250RJ3SR-L, AT24C01A/02/04/08/16 88E1111
2006 - Alaska Ultra 88E1111 Integrated Gigabit Ethernet

Abstract: 88E1111 88E1111 schematic Marvell PHY 88E1111 schematic Marvell PHY 88E1111 layout 88e1111 Power Current Marvell 88E1111 specification Marvell PHY 88E1111 Datasheet footprint Marvell PHY 88E1111 Datasheet Marvell 88E1111
Text: programmed via two-wire interface with the device address 0xA6. For details of PHY IC registers in 88E1111 , with SGMII interface by reconfiguration of the PHY within the SFP. 2. This part uses the SFP's Rx-Los , can operate in 10/100/1000 Base-T with SGMII interface by reconfiguration of the PHY within the SFP , used to reset the chip of Gigabit Ethernet PHY inside the copper SFP. It is pulled up within the , . 5) Byte 128-255 had been set hex. 00. LCP-1250RJ3SR Internal PHY Register (Two-Wire Address


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PDF LCP-1250RJ3SR 1000BASE-T) 1000BASE-X) RJ-45 LCP-1250RJ3SR 1250Mb/s, LCP-1250RJ3SR-S, AT24C01A/02/04/08/16 88E1111 Alaska Ultra 88E1111 Integrated Gigabit Ethernet 88E1111 schematic Marvell PHY 88E1111 schematic Marvell PHY 88E1111 layout 88e1111 Power Current Marvell 88E1111 specification Marvell PHY 88E1111 Datasheet footprint Marvell PHY 88E1111 Datasheet Marvell 88E1111
2006 - Marvell 88E1111

Abstract: No abstract text available
Text: had been set hex. 00. LCP-1250RJ3SR Internal PHY Register (Two-Wire Address 0xA6) LCP-1250RJ3SR is internally designed of physical layer IC (Marvell 88E1111 ), which can be programmed via two-wire interface with the device address 0xA6. For details of PHY IC registers in 88E1111 , see Marvell document “Alaska Ultra 88E1111 Integrated Gigabit Ethernet Transceiver”. 7 DELTA ELECTRONICS, INC. May , tied to ground. TX disable is an input that is used to reset the chip of Gigabit Ethernet PHY inside


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PDF LCP-1250RJ3SR 1000BASE-T) 1000BASE-X) RJ-45 LCP-1250RJ3SR 1250Mb/s, LCP-1250RJ3SR-S, AT24C01A/02/04/08/16 88E1111 Marvell 88E1111
2012 - Not Available

Abstract: No abstract text available
Text: ® functions with on-board Marvell 88E1111 PHY chips. The reference designs provide flexible test and , ) rgmii_rx USR_LED2 USR_LED3 rgmii_tx RX TX 88E1111 PHY External Ethernet Packet Generator , sgmii_tx RX TX 88E1111 PHY External Ethernet Packet Generator Notes to Figure 2: (1) M = , Ethernet and On-Board PHY Chip Reference Design Page 10 Base Addresses and Configuration Registers , – Marvell PHY configuration setting—allows you to configure the on-board PHY chip registers . ■â


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PDF AN-647-1 88E1111
2007 - 88E1111 schematic

Abstract: 88E111* HWCFG_MODE sgmii 88E1111 88e1111 registers 0xac Marvell PHY 88E1111 layout Marvell PHY 88E1111 88E1111 mac address 88E1111 register 88e1111 Power Current sgmii mode sfp
Text: with the device address 0xAC. For details of PHY IC registers in 88E1111 , see Marvell document "Alaska , software can configure the PHY device inner LCP-1250RJ3SR-L via SFP two-wire-inter- face. LCP , Internal PHY IC is configurable by host system software via SFP 2-wire-interface Applications Gigabit , by reconfiguration of the PHY within the SFP. 3. This part supports the 10/100/1000 Base-T with SGMII interface by default. Serial Interface Configuration ( PHY Two-Wire Address 0xAC) Register 27 Bits 3:0


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PDF LCP-1250RJ3SR-L GBIC-1250RJ3SR, 1250Mb/s, LCP-1250RJ3SR-S, AT24C01A/02/04/08/16 88E1111 88E1111 schematic 88E111* HWCFG_MODE sgmii 88E1111 88e1111 registers 0xac Marvell PHY 88E1111 layout Marvell PHY 88E1111 88E1111 mac address 88E1111 register 88e1111 Power Current sgmii mode sfp
2011 - Marvell PHY 88E1111 altera

Abstract: marvell 88E1111 register RGMII cyclone IV altera ethernet packet generator SGMII RGMII bridge programming 88E1111 marvell 88E1111 register RGMII triple-speed ethernet 88E1111 Marvell PHY 88E1111 88E1111 cyclone
Text: ® functions with on-board Marvell 88E1111 PHY chips. The reference designs provide flexible test and , TX 88E1111 PHY External Ethernet Packet Generator Notes to Figure 1: (1) M = Avalon-MM Master , 88E1111 PHY External Ethernet Packet Generator Notes to Figure 2: (1) M = Avalon-MM Master Port , Marvell PHY registers in the reference designs. You can configure the following settings in the Tcl , registers . PHY_ETH_SPEED-select the PHY 's operating speed. PHY_ENABLE_AN-use this


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PDF AN-647-1 88E1111 Marvell PHY 88E1111 altera marvell 88E1111 register RGMII cyclone IV altera ethernet packet generator SGMII RGMII bridge programming 88E1111 marvell 88E1111 register RGMII triple-speed ethernet Marvell PHY 88E1111 88E1111 cyclone
2006 - Marvell PHY 88E1111 layout

Abstract: Marvell PHY 88E1111 schematic 88E1111 full 88e1111 SGMII mode 88E1111 layout sfp autonegotiation Marvell PHY 88E1111 0xac Alaska Ultra 88E1111 Integrated Gigabit Ethernet 88e1111
Text: registers in 88E1111 , see Marvell document "Alaska Ultra 88E1111 Integrated Gigabit Ethernet Transceiver , -1250RJ3SR-L supports RX_LOS enabled Internal PHY IC is configurable by host system software via SFP 2 , software to configure MAC on host system. At enhance, the software can configure the PHY device inner LCP , by reconfiguration of the PHY within the SFP. 2. This part uses the SFP's Rx-Los pin for link , /1000 Base-T with SGMII interface by reconfiguration of the PHY within the SFP. 3. This part supports


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PDF LCP-1250RJ3SR-L LCP-1250RJ3SR-L 1000Mb/s 1250Mb/s, LCP-1250RJ3SR-S, AT24C01A/02/04/08/16 88E1111 Marvell PHY 88E1111 layout Marvell PHY 88E1111 schematic 88E1111 full 88e1111 SGMII mode 88E1111 layout sfp autonegotiation Marvell PHY 88E1111 0xac Alaska Ultra 88E1111 Integrated Gigabit Ethernet
2005 - 88E6095F

Abstract: 88e6095 88E6185 88e6218 marvell 88E6185 marvell 88e6 marvell 88E6095f Marvell 88E1111 88E6092 marvell marvell switch 88e6095
Text: Address Table Switch Registers SW_MODE[1:0] 4,096 Entry 802.1Q VLAN Table PHY Polling Unit , ) SMI_PHY SMI_PHY 8 8 FE SERDES FE 1 GE Alaska GbE PHY ( 88E1111 ) SERDES Alaska GbE PHY ( 88E1111 ) SMI 1 GE Fig 2. 88E6095-Based 24-Port 10/100 + 2-Port GbE Layer 2 , Slot Port Controller P0_TX 28 32-Bit and 2 64-Bit RMON Counters per Port External PHY Reg Interface MDC_PHY MDIO_PHY MAC or PHY Mode MII Interface P10_TX Fiber Enable and Controls P10_RX


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PDF 88E6092/88E6095/88E6095F 88E6092/88E6095/88E6095F 10BASE-T/ 100BASE-TX 88E6092/88E6095 88E6092 88E6092/95/95F-001 88E6095F 88e6095 88E6185 88e6218 marvell 88E6185 marvell 88e6 marvell 88E6095f Marvell 88E1111 88E6092 marvell marvell switch 88e6095
2003 - 88E1111 RGMII

Abstract: Marvell PHY 88E1111 Datasheet Xilinx Marvell 88E1111 vhdl Marvell PHY 88E1111 alaska rgmii specification 88E1111 RGMII phy Xilinx 88E1111 verilog RGMII Marvell PHY 88E1111 Datasheet
Text: required to connect the Gigabit Ethernet MAC to a Gigabit PHY from 24 to 12. The RGMII achieves this 50 , daughter card that contains a Marvell Alaska 88E1111 10/100/1000 Mb/s transceiver in RGMII mode connected , ] RGMII_TXD[3:0] GMII_TX_EN RGMII_TX_CTL GMII_TX_ER RGMII_TX_CLK GMII_TX_CLK PHY RGMII_RXD , RGMII FPGA External PHY X692_01_102903 Figure 1: High-Level Block Diagram The GMII_TX_CLK , negative edge of the RGMII_TX_CLK clock. The outputs of these two registers go to the FDDRRSEs that


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PDF XAPP692 DS200, 1000BASE-X) 88E1111 RGMII Marvell PHY 88E1111 Datasheet Xilinx Marvell 88E1111 vhdl Marvell PHY 88E1111 alaska rgmii specification 88E1111 RGMII phy Xilinx 88E1111 verilog RGMII Marvell PHY 88E1111 Datasheet
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